Top Senior Level Semiconductor Jobs in Austin, TX

Lead architecture and development of OpenBMC firmware for AI infrastructure, collaborating with partners on reliability, scalability, and serviceability.

Design, develop, and deploy UEFI-based firmware for hyperscale AI server platforms, ensure platform integration, and implement security features.

Lead the hardware validation for Graphcore's AI platforms, define validation strategies, and manage a team of hardware validation engineers to ensure products meet quality and reliability standards.

Lead and drive licensing strategies for semiconductor IP portfolio, collaborating with teams, engaging clients, negotiating agreements, and managing contract lifecycle.

The role involves developing and maintaining testing processes for semiconductor equipment, troubleshooting issues, and implementing machine learning models.

The Senior Manager for Insider Risk Detection & Response oversees the insider risk program, manages a team, and collaborates with various departments to mitigate insider threats.

Support internal and external attorneys with litigation matters, focusing on e-discovery, document collection, and legal notices management. Requires excellent problem-solving and organizational skills in a fast-paced environment.

The Product Marketing Manager develops and executes go-to-market strategies for CMOS products, focusing on positioning, messaging, launches, and sales enablement while engaging with market insights and cross-functional teams.

As a Product Manager for our CMOS product line, you'll oversee product strategy, market discovery, requirements, and cross-functional collaboration to ensure product success.

The role involves building and optimizing embedded AI runtimes, implementing ML operator kernels, and improving performance for on-device AI in resource-constrained environments.

Develop reliable, scalable software tools for DFT/ATPG, enhancing efficiency in software architecture and algorithms as part of a team.

The role involves defining verification strategies for complex SoCs, implementing UVM-based environments, and ensuring full coverage and functional correctness through collaboration with diverse engineering teams.

Define verification strategies for complex SoCs, architect UVM-based environments, ensure exhaustive verification, debug simulations, and collaborate across teams to improve methodology.

The Senior Verification Engineer will verify digital design blocks, build verification environments using SystemVerilog and UVM, and work closely with design engineers.

The Master Planner at UCT will create an operations plan, align customer demand with supplier capacity, maintain configurations in MRP, identify risks, and support schedule execution while collaborating with various teams.