Jobs at Broadcom

Lead complex ASIC implementation projects across synthesis, design-for-test, floorplanning, place and route, clock methodology, power analysis, timing closure, signal integrity, and physical design verification. Lead design-closure disciplines, adapt across multiple EDA vendor solutions, drive peer reviews, and collaborate with globally distributed customers and design teams. Work independently on technically complex projects while setting direction for other team members.

Leads Broadcom’s local DFT team through ASIC and SoC DFT architecture, insertion, verification, pattern generation, coverage improvement, silicon debug, and yield improvement. Manages DFT resources, collaborates with physical design, STA, manufacturing, test, customers, and global stakeholders, and performs hands-on technical support. Oversees DFT specifications, timing closure, failure analysis, staff development, and product release activities.

Designs and implements DFT for SoCs from specification through production release. Responsibilities include scan, MBIST, TAP, LBIST, IO, SerDes, ATPG, test vector generation and verification, test timing closure, silicon bring-up, failure analysis, diagnostics, yield improvement, and customer-return debugging. Collaborates with physical design, STA, test engineering, manufacturing, customers, and global stakeholders.

Designs and implements SoC DFT features including scan, MBIST, boundary scan, LBIST, ATPG, and IJTAG. Generates and debugs test vectors, improves coverage and yield, supports timing closure, and validates silicon on ATE. Performs post-silicon failure analysis and customer-return debugging while collaborating with physical design, test, manufacturing, customers, and global engineering teams.

Lead DFT programs from architecture and specification through implementation, verification, tape release, silicon bring-up, debug, and production yield improvement. Implement and verify scan, ATPG, MBIST, boundary scan, LBIST, TAP, IO, and SerDes DFT. Generate and debug test vectors, close test timing with physical design and STA teams, automate DFT flows, support ATE validation, analyze silicon failures, and collaborate with customers and global engineering teams.

Design complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G applications. Responsibilities include package layout, signal and power integrity, thermal performance, reliability, manufacturability, project scheduling, customer interface, and collaboration with internal and vendor teams. The role also supports process improvement, documentation, automation, and multi-project execution.

Lead the architecture, deployment, and scaling of agentic AI infrastructure for embedded memory design, characterization, DFT, silicon bring-up, and yield optimization. Develop multi-agent LLM workflows, integrate AI systems with EDA tools and enterprise data, automate scan-failure analysis, build predictive yield models, and establish evaluation, testing, and safety guardrails. Collaborate with memory designers, DFT experts, EDA specialists, and infrastructure engineers to deliver production-grade AI engineering solutions.

Develops and deploys Calibre verification decks for advanced FINFET, GAA, and high-voltage technologies. Defines tool acceptance criteria, creates IP test cases and test structures, automates CAD workflows, supports extraction and simulation tools, resolves EDA and technology-file issues, documents processes, trains design engineers, and evaluates emerging EDA capabilities. The role collaborates with foundries, EDA vendors, and internal engineering teams to support physical verification and post-layout extraction.

Design, deploy, and optimize autonomous multi-agent AI architectures for semiconductor IP block development and support workflows. Integrate LLM orchestration and Model Context Protocol systems with enterprise verification frameworks to improve efficiency, quality, and automation across hardware engineering processes.

Provides senior-level technical consulting for mainframe infrastructure environments and Broadcom Software products. Responsibilities include solution architecture, product implementation and upgrades, integrations, demonstrations, proofs of concept, troubleshooting, technical documentation, customer presentations, and post-implementation support. The consultant advises clients and management on infrastructure strategies and works with account teams to design solutions. Requires expertise in z/OS, Broadcom mainframe tools, REXX or HLASM, and major mainframe subsystems and security managers. Client-site travel is required.

Designs complex flip-chip BGA packages for high-performance ASICs used in AI, networking, HPC, and 5G applications. Responsibilities include package layout, signal and power integrity, thermal and reliability considerations, manufacturability, and design of SerDes, ADC/DAC, DDR, and related structures. The engineer manages multiple projects, collaborates with global teams and vendors, interfaces with customers, and improves design processes through automation and documentation. This is a fully onsite role.

Design and architect high-speed 100G+ SerDes signal-processing systems, including equalizers, FEC, filters, modulation, and analog compensation. Develop MATLAB and C/C++ models, simulations, requirements, verification plans, firmware, and lab tests. Collaborate with analog, digital, RTL, firmware, and validation teams to implement and debug ASIC designs. Support communications standards development, customer meetings, technical documentation, and marketing collateral.

Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.

Design and verify high-speed SerDes physical-layer algorithms and architectures (100G+). Develop bit-exact MATLAB and C/C++ system models, run system-level simulations, collaborate with analog/digital teams, perform lab validation and firmware/debug, document requirements and test plans, support standards and customer interactions.

Design and deliver high-performance flip-chip BGA ASIC packages addressing signal integrity, power integrity, thermal, reliability, and manufacturability. Perform physical layout, manage multiple projects, interface with customers and vendors, and improve design processes and automation.