Jobs at Broadcom

Design and verify high-speed SerDes physical-layer algorithms and architectures (100G+). Develop bit-exact MATLAB and C/C++ system models, run system-level simulations, collaborate with analog/digital teams, perform lab validation and firmware/debug, document requirements and test plans, support standards and customer interactions.

The Principal Kubernetes Software Engineer will design and develop features for Kubernetes, contribute to CNCF projects, lead teams, and mentor engineers while ensuring adherence to architecture, security, and compliance standards.

The role involves designing and implementing software enhancements for VCF, full stack development, and participating in operational support and CI pipeline improvements.

Develop system software for converged appliance platforms, implement enhancements, full stack development, and provide operational support. Collaborate with teams and improve system performance through test-driven development and CI pipelines.

Lead design and implementation of an AI Virtualization Stack for ESXi, integrating PyTorch/JAX backends via OpenXLA. Optimize ML acceleration (LLM inference, KV-caching, FlashAttention), troubleshoot GPU/XPU runtime issues, collaborate with driver/device teams and vendors, and deliver production-quality code and documentation.

Develop innovative IT solutions, participate in agile development, conduct code and test plan reviews, ensuring high-quality software delivery.

Senior mainframe infrastructure consultant providing architecture, implementation, upgrades, troubleshooting, demos/POCs, and technical leadership for Broadcom mainframe products. Requires coding/scripting (REXX/COBOL/HLASM), deep z/OS expertise, customer engagement, and travel to client sites.

Design and deliver high-performance flip-chip BGA ASIC packages addressing signal integrity, power integrity, thermal, reliability, and manufacturability. Perform physical layout, manage multiple projects, interface with customers and vendors, and improve design processes and automation.

Design and verify front-end RTL blocks for ASIC cores: define architecture, implement logic, perform synthesis, constraints, simulation and formal verification, analyze timing from physical implementation, debug Verilog designs, and collaborate across global teams within the full ASIC implementation flow.

Responsible for front end design and verification of ASIC design blocks, including architecture definition, logic design, synthesis, and verification through simulation and analysis of timing.

The role involves designing flip-chip-BGA packages for ASICs, collaborating on designs, managing projects, and improving processes.

Perform DFT tasks including MBIST and scan insertion, ATPG and pattern simulation, ATE pattern development and silicon debugging, yield analysis, and cross-functional DFT collaboration during design and silicon bring-up.