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Cadence Design Systems

Principal AE (STA - SignOff)

Reposted 12 Days Ago
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In-Office
Austin, TX, USA
116K-216K Annually
Expert/Leader
In-Office
Austin, TX, USA
116K-216K Annually
Expert/Leader
Provides pre-sales and post-sales technical support for Cadence digital implementation and signoff tools. Delivers customer workshops, benchmarks, demonstrations, methodology consultations, technical evaluations, and product support. Partners with sales teams on technical campaigns, supports customer implementations and usage expansion, collaborates with R&D on methodology improvements, and creates technical content. Requires expertise in digital design, semiconductor fundamentals, static timing analysis, ASIC implementation flows, scripting, and customer-facing problem solving.
The summary above was generated by AI
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for a Principal Application Engineer responsible for providing pre-sales and post-sales technical support for the Digital Implementation and Signoff tools. The candidate will work closely with sales executives in supporting sales campaigns by delivering workshops, benchmarks, product demonstrations, methodology consultations and product support. 


Position also involves:

•    Presenting to customers the technical capabilities of Cadence Digital Implementation and Signoff tools and flows (Synthesis, Place and Route, Timing/Physical/Power Signoff).

•    Recognizing opportunities for products at existing customers or potential customers, and working with account team to define and execute technical campaigns

•    Support technical evaluations/benchmarks and drive the process to deliver Cadence solutions implementations

•    Ongoing support and usage proliferation at existing customers (on/offsite)

•    Working closely with R&D on tools and methodology improvements

•    Create and contribute technical content for Cadence Online Support

•    Travel as required (up to 20%)


The Position Requirements are…

  • Minimum BS-EE plus 8 to 10 year’s experience or MS-EE, plus 6 to 8 year’s experience, Core timing signoff expertise, advanced node STA, UPF & constraints debugging, hierarchical & 3DIC design STA and closure solutions
  • Digital Design Fundamentals, Semiconductor fundamentals and  Static Timing Analysis is required
  • Experience with ASIC digital implementation flows and tools
  • Working knowledge of a scripting language TCL/Perl/Python
  • Candidate should have strong customer-facing communication and problem solving skills
  • Strong personal drive for continuous learning and expanding professional skill sets
  • Strong verbal and written communication skills

The annual salary range for California (Other than San Jose) is $116,200 to $215,800. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure.Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

Cadence Design Systems Austin, Texas, USA Office

Austin, United States

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