Top Design Engineer Jobs in Austin, TX

Design CMOS SRAM and ROM circuits and periphery to meet compiler performance, power, and area targets. Create and run simulation characterization and testbenches, work with layout and CAD teams, ensure frontend model alignment, and collaborate globally to share methodologies and implement GenAI/EDA efficiencies.

Designs and delivers EPMS, electrical telemetry, and industrial controls solutions for Microsoft AI datacenters. Responsibilities include defining instrumentation and communications requirements, configuring EPMS hardware and networks, developing system integrations, testing and commissioning technologies, troubleshooting complex electrical and controls issues, producing technical documentation, and coordinating with multidisciplinary engineering, vendor, commissioning, and deployment teams.

Designs and implements privacy-by-design controls across enterprise data platforms, analytics, AI systems, digital products, and connected vehicle technologies. Develops privacy-preserving solutions including pseudonymization, tokenization, encryption, masking, consent management, access controls, and data minimization. Partners with Engineering, Legal, Privacy, Cybersecurity, Product, and Data Governance teams to embed privacy requirements into software and vehicle development lifecycles. Supports standards, assessments, audits, control validation, remediation, and technical guidance.

Design end-to-end production machines: mechanisms, end effectors, fixtures, and tooling in Onshape. Prototype with 3D printing and machining, integrate motion, actuators, controls, and vision, then bring machines to production, measure cycle time and reliability, and iterate to improve performance and manufacturability.

Performs CPU physical design from RTL through GDS, including synthesis, floor planning, placement and routing, clock tree synthesis, timing closure, power and reliability analysis, and signoff verification. The role optimizes CPU designs for power, frequency, and area; collaborates with architecture, logic, circuit, automation, and EDA vendor teams; develops physical design methodologies; and supports tapeout on advanced process technologies.

Lead FPGA design, implementation, verification readiness, and hardware bring-up for complex server, storage, networking, and AI infrastructure platforms. Provide technical ownership of FPGA architecture and RTL, lead lab debug and validation using lab equipment, resolve cross-domain integration issues, manage schedules and risks, mentor junior engineers, and communicate technical direction to stakeholders.

Lead BIOS/UEFI firmware development and platform integration across product platforms. Provide technical ownership for firmware features, debug complex issues, optimize performance, ensure validation and manufacturing readiness, collaborate with cross-functional teams, mentor junior engineers, and communicate technical direction and risks to leadership.

Implements and optimizes CPU physical designs from RTL through manufacturing-ready databases. Responsibilities include floorplanning, synthesis, place and route, clock tree synthesis, static timing analysis, power optimization, verification, signoff, layout checks, and design automation. The engineer collaborates with architecture, logic, circuit, validation, automation, and EDA teams to improve performance, power, area, timing, manufacturability, and physical design methodologies.

Design and implement FPGA code for satellite digital payloads, including DSP algorithms, software-defined radio modulation and demodulation, and embedded processor interfaces. Develop custom IP, improve DSP and interface reliability, integrate vendor IP, and support communications architecture and spacecraft design studies. Participate across simulation, synthesis, place and route, timing closure, and hardware testing using Xilinx FPGAs and industry-standard HDL and simulation tools.

Designs analog circuits for MRAM memory products, including sense amplifiers, drivers, charge pumps, bandgaps, regulators, oscillators, and bias networks. Develops low-power, low-noise, high-precision designs; performs circuit, post-layout, and top-level verification; supports tape-out and layout integration. Collaborates with product and test engineers on test plans, lab results, bug fixes, and yield improvements, while documenting simulations and design reviews.

Design, develop, and validate mechanical and electromechanical test fixtures and ATE for PCBAs and assemblies. Create 3D CAD models and manufacturing drawings, manage BOMs/ECOs, prototype and test fixtures, support supplier fabrication and CNC operations, and collaborate cross-functionally to deploy scalable, manufacturable test solutions while mentoring junior staff.

Design, implement, analyze, and optimize clock distribution networks for high-performance CPU and SoC products. Responsibilities include clock architecture, clock tree synthesis, timing analysis and closure, custom circuit and library-cell development, power-performance-area optimization, automation scripting, and collaboration across architecture, physical design, validation, and EDA teams.

Designs and develops advanced memory circuits, including SRAMs, caches, register files, ROMs, and custom memory IP for CPU and SoC products. Responsibilities include circuit simulation, characterization, PPA optimization, variation analysis, memory path-finding, and collaboration with architecture, process, physical design, and product engineering teams.

Execute synthesis, place and route, static timing analysis, and physical verification for ASIC partitions. Collaborate with architecture, RTL, DFT, and methodology teams to resolve implementation and signoff issues, close EM/IR, drive LEC, and improve physical design flows. Troubleshoot EDA workflows, work with vendors, implement low-power techniques, and develop custom TCL scripts for Cadence and Synopsys tools. The role is fully onsite in San Jose, California.

Perform physical mask layout for mixed-signal circuits, including PLLs, high-speed I/O, general I/O, and ESD structures, using Cadence tools and advanced CMOS technologies. Collaborate with ASIC and mixed-signal engineers on floor planning, custom layout, top-level integration, and design verification. Run and debug DRC/LVS checks, customize verification decks, and support tape-outs using FinFET technologies.

Design and develop digital subsystems and DSP intellectual property for mixed-signal SoCs, from architecture and RTL through tape-out. Responsibilities include subsystem integration, complex state-machine design and verification, clock and reset domain crossing, synthesis, timing constraints, and post-silicon validation, characterization, and product testing. The role supports high-performance ICs incorporating ARM MCUs, serial interfaces, ADCs, and DACs.

Designs and develops hardware test boards and platforms for high-speed electro-optical device characterization in R&D and manufacturing environments. Performs laboratory testing, analog design and debugging, test-system development, hardware bring-up, and firmware development for microcontrollers. Supports System-on-Chip optical engine development and interfaces with vendors. Preferred experience includes power supply design, advanced PCB stack-ups, optical instrumentation, automated measurements, and coherent optical communications.

Leads DFM and DFA analysis for complex PCB assemblies, develops manufacturing rule sets, reviews fabrication and assembly data, and collaborates with manufacturing, quality, engineering, and customers. Designs high-density multilayer PCB layouts from schematics using industry-standard CAD tools, creates manufacturing deliverables, maintains libraries and design standards, and supports continuous improvement across a global electronics manufacturing organization.

Develops detailed audiovisual system designs, including signal flows, schematics, rack layouts, networked AV solutions, technical drawings, and bills of materials. Collaborates with sales, project managers, architects, clients, and engineering teams to refine requirements and support implementation. Conducts design reviews, quality checks, troubleshooting, system validation, and value engineering while ensuring designs meet project scope, budget, standards, and client expectations.

Designs and validates electrical and electronic components, subsystems, integrated circuitry, and hardware solutions. Develops test plans covering tolerances, form, fit, function, shock, vibration, EMI, safety, reliability, thermal performance, and power. Performs feasibility, margin, validation, modeling, and empirical analyses; collaborates with internal and outsourced engineering partners; evaluates production reliability and supports prototype fabrication for reliable, cost-effective products.

Design and characterize high-performance mixed-signal integrated circuits in CMOS processes. Responsibilities include assisting with circuit design, simulation, verification, silicon prototype testing, performance analysis, and design improvements while collaborating with experienced engineering teams. The internship is full-time for 12–16 weeks and requires in-office participation, potentially up to five days per week.

Design and implement Verilog RTL modules for mixed-signal ICs, including DSP and data conversion circuits. Perform simulation, functional verification, synthesis, system integration, behavioral modeling, test-vector generation, and lab test development. The internship is full-time for 12–16 weeks and requires collaboration in an in-office environment.

Build and ship interactive creative and engineering tools using React and TypeScript. Design core interactions, visual systems, motion behavior, accessibility, and performance-focused UI. Partner with internal users to iterate on features, contribute to design systems, review code and designs, and bridge design and engineering. The role requires strong visual craft, interaction design expertise, production engineering skills, and experience delivering complex editors or interactive platforms.

Develop and lead RF, SerDes, and mm-wave integrated circuits from architecture and simulation through silicon validation. Responsibilities include RF and analog IP design, layout guidance, characterization strategy, PCB development, RF and system-level measurements, competitive benchmarking, technology collaboration, productization, and university research liaison activities.

Lead the design and engineering of an AI-powered product that converts Figma design systems into structured context and generates faithful designs back into Figma. Own the encoding pipeline, prompt systems, onboarding and self-serve experience, product surface, and production-quality frontend. Collaborate with product engineers to improve output reliability, reduce nondeterminism, establish evaluation methods, and scale the product across brands and AI models.