Top Design Engineer Jobs in Austin, TX

Design and integrate SoC IPs from architectural specifications; perform Lint and CDC checks; develop synthesis constraints and optimize power, performance, and area. Create microarchitectural specifications, support verification and physical design teams, and automate repetitive tasks using scripting. Collaborate across teams to execute projects effectively.

Develop and deploy internal ASIC design tools, RTL generation workflows, verification utilities, and methodologies across NVIDIA engineering teams. Maintain DevOps-style automated RTL generation operations, support reusable design blocks, and integrate workflows into IP development environments. Requires digital design and Verilog expertise, Python or Perl scripting, Unix/Linux shell scripting, and Makefiles. Experience with ASIC verification, clocks/resets, CDC flows, synthesis, and timing is advantageous.

Design end-to-end production machines: mechanisms, end effectors, fixtures, and tooling in Onshape. Prototype with 3D printing and machining, integrate motion, actuators, controls, and vision, then bring machines to production, measure cycle time and reliability, and iterate to improve performance and manufacturability.

Supports semiconductor physical design through layout implementation, design checks, timing, power, quality, and rule-check activities under senior guidance. Collaborates with design, verification, and methodology teams to resolve issues, improve design quality, document workflows and results, and contribute to project milestones while developing technical expertise.

Supports design-for-test development for microprocessor-based SoCs from test requirements through production. Responsibilities include creating and debugging structural test patterns, pre- and post-silicon verification, ATE pattern conversion, built-in self-test implementation, test coverage analysis, and collaboration with Test Engineering, Product Engineering, and fabrication teams.

Supports digital design implementation, coding, reviews, debugging, checks, simulations, and technical documentation under senior engineer guidance. Collaborates with verification, physical design, and validation teams throughout project execution. Requires a recent engineering or computer science degree, foundational engineering and testing knowledge, strong problem-solving and documentation skills, and clear English communication. Relevant lab work, coursework, internships, design projects, and familiarity with engineering or verification tools are advantageous.

Supports digital design implementation, logic coding, reviews, debugging, checks, simulations, documentation, and test-result maintenance under senior-engineer guidance. Collaborates with verification, physical design, and validation teams throughout project execution while developing engineering, testing, problem-solving, and communication skills.

Designs high-performance silicon and AI system-on-chip components, including IP microarchitecture, RTL, synthesis, and SoC integration. Collaborates with architecture, verification, and physical design teams to ensure implementations meet specifications. The role involves digital design, ASIC/SoC development, clock-domain-crossing and lint closure, PPA trade-offs, fabric or networking ASIC design, and post-silicon debugging.

Intern will perform synthesis, floorplanning, place and route, clock insertion, timing analysis, and timing closure for complex ASIC and processor logic blocks. Responsibilities include scripting in Python, TCL, Perl, and Shell; debugging design violations with EDA tools; and collaborating with RTL, synthesis, and design teams to resolve congestion and timing bottlenecks. The role supports designs meeting performance, power, and area requirements.

Support physical design of ASIC and processor logic blocks through synthesis, floorplanning, place and route, clock insertion, timing analysis, and timing closure. Write scripts in Python, TCL, Perl, and Shell, use industry-standard EDA tools, debug design violations, and collaborate with RTL, synthesis, and design teams to resolve congestion and timing issues.

Lead memory subsystem and complex SoC design from architecture and microarchitecture through silicon bring-up. Develop and integrate RTL, optimize performance, power, bandwidth, and latency, and collaborate across verification, physical design, DFT, firmware, and post-silicon teams. Provide technical leadership, mentor engineers, drive IP reuse, debug system issues, and ensure design-quality closure using simulation, emulation, synthesis, timing, lint, CDC, and RDC processes.

Designs and develops advanced full-custom and compiler-based memory circuits, including SRAMs, caches, register files, ROMs, and custom memories. Responsibilities include circuit simulation, characterization, cache and critical-path analysis, memory architecture, bit-cell and peripheral design, automation, PPA optimization, methodology development, and cross-functional execution for advanced CMOS CPU and SoC products.

Lead integration of full-chip or major SoC subsystems, owning top-level flows and cross-domain decisions across DFT, power, timing, and interconnect architecture. Partner with architecture, RTL, physical design, verification, and DFT teams to resolve system tradeoffs. Support organizational growth through hiring and mentoring while remaining hands-on with advanced-node, high-bandwidth, low-power chip designs.

Collaborate with product designers to implement modular, reusable React components and pixel-perfect UI across desktop and mobile. Build performant CSS-driven interactions, animations, and micro-interactions. Bridge front-end logic with design and maintain high polish across Vetcove's applications.

Own end-to-end electrical hardware development for semiconductor fabrication machines, including clean-sheet PCBA and electrical system design, schematic capture, layout, prototyping, bring-up, testing, integration, documentation, and productionization. Collaborate with software, mechanical, and process teams; investigate design approaches; perform analysis and simulations; and deliver reliable systems autonomously from concept through small-scale production.

Designs and develops custom digital CPU circuits, including memories and caches. Performs floorplanning, schematic entry, simulation, verification, and optimization for power, performance, area, timing, leakage, robustness, and yield. Develops DFT models, memory test tools, and automated design flows. Collaborates with architecture, layout, and cross-functional teams to resolve CPU design issues and characterize memory instances and compilers.

Lead end-to-end PCIe IP integration into complex ASIC and SoC designs, collaborating across architecture, verification, physical design, software, and external IP vendors. Optimize PCIe performance, contribute to IO and interconnect architecture, and lead silicon bring-up, interoperability testing, and debugging across RTL, gate-level, emulation, and post-silicon environments. Mentor engineers and establish PCIe subsystem development practices for high-performance AI and HPC platforms.

Designs and optimizes custom and compiler-based embedded memory solutions for high-performance, low-power CPUs and SoCs. Responsibilities include SRAM, cache, register file, ROM, memory array, bit-cell, and peripheral circuit design; characterization and simulation; critical-path analysis; PPA optimization; automation; methodology development; and cross-functional collaboration with architecture, layout, process, physical design, and validation teams.

Design and architect high-speed 100G+ SerDes signal-processing systems, including equalizers, FEC, filters, modulation, and analog compensation. Develop MATLAB and C/C++ models, simulations, requirements, verification plans, firmware, and lab tests. Collaborate with analog, digital, RTL, firmware, and validation teams to implement and debug ASIC designs. Support communications standards development, customer meetings, technical documentation, and marketing collateral.

Own complex ASIC and SoC physical implementation from synthesized netlist through signoff, including floorplanning, placement, CTS, routing, timing closure, ECOs, physical verification, and power integrity. Lead cross-functional timing and implementation convergence, develop automation and methodologies, resolve advanced-node challenges, and provide technical mentorship. Partner with RTL, architecture, DFT, verification, package, and SI/PI teams while driving PPA, runtime, quality, and tapeout readiness.

Provide engineering support and design for LAN/WAN/WLAN/SD-WAN, Meraki and VPN across ~1,400 locations. Troubleshoot, optimize, document, and secure network infrastructure, manage load balancers (F5), firewalls, and participate in disaster recovery, compliance (SOX/PCI), and cross-team incident response.

Own end-to-end digital design verification for complex SoCs at block, subsystem, and full-chip levels. Develop UVM/SystemVerilog testbenches, verification plans, constrained-random and directed tests, scoreboards, coverage models, and C/C++ SoC validation libraries. Automate regressions and reporting, debug failures, perform root-cause analysis, and collaborate with architecture, design, and software teams. The role requires managing verification milestones, risks, and deliverables through multiple successful tape-outs.

Design and develop high-speed photonic integrated circuit devices. Perform RF and electro-optical simulations (HFSS, ADS), execute electrical/optical s-parameter testing, create designed experiments, analyze large datasets, and collaborate with fab, test, reliability, packaging, system, and product engineering to ensure device performance and reliability.

Lead architecture, design, fabrication, testing, and optimization of silicon photonics integrated circuits for coherent long-haul, metro, and pluggable optical systems. Drive PIC specification, link-budget analysis, DFM/DFT practices, cross-functional execution with RFIC/DSP/packaging/foundry partners, and establish simulation and test infrastructures for scalable, high-yield production.

Design Engineering Intern supporting Food and Beverage R&D through concept ideation, product architecture, validation testing, 3D CAD development in SolidWorks, technology and manufacturing-partner research, and progress reporting to engineering leadership.