Top Design Engineer Jobs in Austin, TX

The CPU Physical Design Engineer will implement custom CPU designs, conduct physical design flow, optimize designs, and collaborate on verification processes. They will work with EDA vendors and enhance methodologies for CPU design.

As a CPU Physical Design Engineer, you'll implement custom CPU designs from RTL to GDS and conduct all aspects of the physical design flow including synthesis, place, and route. You'll verify designs and collaborate with various teams to enhance microarchitectures.

The role involves performing physical design implementation, conducting verification and signoff, optimizing CPU design, and collaborating with various teams. Key responsibilities include synthesis, place and route, and static timing analysis.

Design and optimize advanced embedded memory IP (SRAM, register files, ROM) for Intel CMOS processes. Perform memory pathfinding, PPA optimization, custom circuit design, layout and automation, pre-silicon verification and post-silicon validation/debug to enable yield and product ramp. Collaborate with domain experts, EDA vendors, and product teams to deliver memory collaterals and test chips.

The CPU Memory Design Engineer will design and develop custom memories and digital circuits for Intel CPUs, focusing on low-power and high-performance memory designs.

Design and develop custom and compiler-based memory circuits including SRAMs and caches, focusing on high-performance and low-power implementations.

Design and integrate SoC logic: develop RTL (SystemVerilog), collaborate on microarchitecture, integrate/validate IPs, optimize for power/performance/timing, support verification and pre-silicon validation, and ensure secure development and production readiness.

Responsible for physical design and implementation of GPUs and ASICs, including methodology establishment, power/clock distribution, and timing closure.

As an ASIC Design Engineer, you will develop methodologies and RTL for performance monitoring of GPUs and SOCs, working alongside senior engineers and team members.

Develop next-generation ASICs for SpaceX's Starlink system, evaluate architectural trade-offs, and ensure design verification and integration with physical implementation teams.

Lead development of custom IP (SRAM and register files) with SoC partners to meet PPA targets. Work with process teams on DTCO, create statistical and timing/power/EMIR characterization methodologies, run QA on IP collateral, define post-silicon testchip characterization plans, and develop scripting automation for flows.

Design, implement, and optimize memory controller micro-architecture in Verilog/SystemVerilog. Integrate IP into SoC, write basic tests, perform lint/CDC/low-power/timing checks, and automate tasks with scripting and AI. Collaborate cross-functionally and with IP providers to deliver high-quality, performance- and power-optimized blocks on schedule.

The Senior Mechanical Design Engineer leads mechanical design for nuclear reactors. Responsibilities include design ownership, engineering analyses, mentoring, and ensuring safety standards.

The Design Engineer will create marketing experiences on Givebutter's Astro-based site, collaborating with the design team to ensure engaging, functional interfaces that reflect the brand's identity.

The Systems Design Engineer at Emerson T&M guides validation testing techniques, defines architectural product requirements, and collaborates with teams to innovate and optimize semiconductor validation systems.

Design and deliver digital IP (RTL) for SoC components using Verilog/SystemVerilog; plan documentation and schedules; collaborate with verification to achieve full coverage; perform quality checks (Lint, CDC, STA); track metrics and support SoC integration, validation, and field issue resolution.

Responsible for analyzing architectural requirements, delivering high-performance RTL blocks, collaborating with engineers, and assisting in IP solution integration.

As a Senior ASIC Design Engineer, you will architect GPU/CPU clock domains, collaborate across teams for design requirements, and improve clocking topologies while ensuring design fixes and silicon debug support.

As a Senior ASIC Design Engineer at NVIDIA, you will improve methodologies and deliver system-level IP for performance measurement in GPUs and SOCs, requiring strong RTL design and verification skills.

Develop and deliver system-level IP and RTL to measure performance on GPUs/SOCs. Create and automate flows, run/debug RTL checks (CDC, clocks, resets, latency), implement RTL features, and collaborate with architects, designers, and software engineers to support projects and performance monitoring.

As an ASIC Clocks Design Engineer, you'll architect clock domains, collaborate across teams, and innovate clocking topologies to enhance GPU and CPU design performance.

Lead floorplan design from early architecture through physical implementation for high-performance SoCs/CPUs/GPUs. Collaborate with cross-functional teams to optimize area, power, timing, and interconnect; develop AI-driven workflows and tools; identify technical risks and drive mitigation to meet product goals.

Design and optimize analog and mixed-signal circuits (power delivery, IPs) for advanced CMOS nodes. Perform circuit simulation, floor-planning, post-layout extraction, verification, and validation. Collaborate with architecture, layout, and validation teams, analyze test data, and iterate designs to meet power, performance, area, timing, yield, and robustness goals.

Design and implement CPU microarchitecture and RTL with emphasis on power management and energy efficiency. Develop SystemVerilog/Verilog RTL, drive PPA optimization, design CDC solutions, support DVFS, power/thermal management, reset and power-state transitions, debug complex RTL, and collaborate with verification, physical design, and SoC integration teams to deliver full-chip solutions.

Perform RTL-to-GDSII physical implementation including synthesis, hierarchical floorplanning, place-and-route, STA, power integrity, CTS, timing ECOs and equivalence checks. Improve EDA tool flows, collaborate with RTL/DFT/EDA vendors, and contribute automation for STA and sign-off across multi-mode/multi-corner scenarios.