Top Design Engineer Jobs in Austin, TX

Design and integrate SoC subsystems (PCIe, DDR/LPDDR, HBM, UCIe, Ethernet); author micro-architecture specs; develop RTL in Verilog; perform static checks (CDC, RDC, X-Propagation, linting); collaborate with verification, performance analysis, and backend teams for floorplanning and timing closure; improve design methodologies and mentor team members while supporting project management.

Design and build frontend experiences and components for the Cloudflare dashboard. Collaborate with design and systems engineers, own code from inception to release, and improve developer experience. Debug, optimize, and identify failure modes in large-scale frontend and distributed systems.

The RTL Design Engineer will design and analyze high-performance interconnects, ensuring they meet functional, performance, power, and area goals.

The Senior Analog Circuit Design Engineer will design and verify analog circuitry for avionics, collaborate with engineering teams, and perform circuit analysis and troubleshooting.

Responsible for designing, testing, and verifying DC/DC and AC/DC power electronics for military and commercial applications, collaborating with multiple engineering disciplines.

The role involves leading the design and testing of complex digital circuit cards. Responsibilities include mentoring junior engineers, interfacing across departments, troubleshooting, and improving design methodologies.

Design, test, and verify DC/DC and AC/DC power electronics for military and commercial aircraft applications, collaborating across multiple disciplines.

Design and test power electronics for military and commercial aircraft, conducting research, troubleshooting, and ensuring compliance with specifications.

As a Senior AI Compiler Engineer, you will design and build a custom MLIR-based compiler stack for next-gen silicon, optimizing AI models without an OS. Responsibilities include creating MLIR dialects, ensuring accuracy in lowering computational graphs, and maintaining a high-performance compiler codebase.

Lead architecture, design, test, and verification of high-reliability high-speed digital circuit card assemblies for avionics and ground vehicle systems. Provide technical leadership through schematic/layout capture, signal integrity analysis, test plan development, environmental and integration testing, troubleshooting, and cross-functional coordination. Mentor junior engineers and interface with customers, suppliers, and operations to drive design closure and production transition.

Lead microarchitecture, RTL development, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink). Translate requirements into synthesizable RTL, collaborate across architecture, verification, firmware, and physical design, analyze traffic and buffering tradeoffs, drive delivery from concept through synthesis and timing closure, mentor engineers, and debug cross-functional issues to meet performance, power, area, and reliability targets.

As a Senior Fullstack Engineer, you'll contribute to backend development for Toast's New Ventures team, collaborating on architecture and launching MVPs while addressing unmet operator needs.

Design and develop primary and secondary structural components for a next-generation UAV. Perform CAD modeling, hand calculations, limited FEA, generate drawings and documentation, support validation and testing, collaborate with cross-functional teams, and iterate hardware through manufacturing and flight tests.

Design and develop primary and secondary structural components for a next-generation UAV platform from concept through production. Create CAD models and drawings, perform hand calculations and basic FEA, collaborate with cross-functional teams for system integration, support structural testing and validation, resolve manufacturing and flight-test issues, and produce engineering documentation in compliance with aerospace standards.

Design and develop primary and secondary structural components for a next-generation UAV. Execute full design lifecycle, perform hand calculations and limited FEA, support structural validation and testing, produce drawings and documentation, and collaborate with cross-functional teams to ensure manufacturability and system integration.

Collaborate with product designers to implement modular, reusable React components and pixel-perfect UI across desktop and mobile. Build performant CSS-driven interactions, animations, and micro-interactions. Bridge front-end logic with design and maintain high polish across Vetcove's applications.

The Senior/Staff Design Verification Engineer will be responsible for design verification in coherent interconnects. Specific responsibilities are not detailed, but expertise in this area is expected.

Perform RTL-to-GDS physical implementation for CPU blocks: synthesis, floorplanning, place-and-route, clock tree synthesis, STA, power/clock distribution, reliability, and noise analysis. Lead verification and signoff (formal equivalence, DRC/LVS, power integrity). Collaborate with logic, circuit, architecture, EDA vendors, and automation teams to optimize power, frequency, and area and improve physical design methodologies and flows.

Lead end-to-end physical design from RTL to GDS for flagship silicon: synthesis, floorplanning, place-and-route, timing signoff, physical verification, EMIR, formal equivalence, and low-power verification. Coordinate across CAD, RTL/DFT, architecture, and power teams to optimize PPA, drive design flows and tooling, mentor engineers, and ensure delivery of production tape-outs.

Design, validate, and implement tooling, jigs, and fixtures from prototype through production. Lead strain testing and material characterization, create and release detailed drawings, support manufacturing with tolerance analysis and design improvements, manage supplier sourcing and project activities for key accounts.

Perform end-to-end CPU physical design from RTL to GDS: synthesis, place-and-route, CTS, floorplanning, STA, power/noise and reliability analysis, verification/signoff (DRC/LVS, formal), and collaborate with architecture, circuit, and EDA teams to optimize power, frequency, and area.

Design, simulate, and validate advanced I/O and ESD protection circuits. Develop silicon test structures for ESD and latch‑up evaluation, translate silicon data into design rules, release and maintain I/O libraries and models, drive chip‑ and block‑level ESD sign‑off, and lead cross‑team ESD and I/O reliability strategy.

As a Physical Design Engineer, you'll implement complex mixed-signal SoCs, optimizing timing and collaborating within a design team, while also developing design methodologies.

Design and implement mixed-signal IP logic: RTL coding, simulation, and optimization to meet power, performance, area, and timing goals. Collaborate with analog, digital, and physical teams, review and fix RTL verification issues, and support SoC customers for high-quality IP integration.

Design and optimize CPU logic and RTL, write and simulate RTL for CPU IP blocks, meet PPA and timing goals, ensure physical design integrity, review verification plans, document microarchitectural specs, and collaborate with SoC customers for integration.