Top Design Engineer Jobs in Austin, TX

Leads architecture, design, testing, verification, integration, and production transition for high-reliability digital circuit cards and modules. Responsibilities include FPGA and microprocessor circuit design, schematic and layout capture, signal integrity analysis, environmental testing, troubleshooting, documentation, defect resolution, customer and supplier coordination, and mentoring junior engineers.

Designs, tests, qualifies, and supports high-reliability DC/DC and AC/DC power electronics for military and commercial aerospace applications. Responsibilities include circuit architecture, component selection, schematic capture, PWB layout, simulation, verification testing, requirements compliance, troubleshooting, root-cause correction, EMI/EMC design, and lifecycle support. The role also advances power electronics technology through research and development and collaborates with systems, hardware, software, test, and operations teams.

Design and develop automated assembly cells, custom tooling, and prototypes for high-volume electronics manufacturing. Create 3D CAD models, drawings, BOMs, and perform tolerance, structural, and cycle-time analyses. Support equipment integration, commissioning, validation, and production launch while collaborating with cross-functional teams and suppliers.

Leads architecture, specification, transistor-level design, verification, layout supervision, validation, and production release of complex analog and mixed-signal IC subsystems. The role addresses power management, clocking, data conversion, advanced-node design, manufacturing test, and post-silicon characterization. It also guides senior engineers, leads technical reviews, resolves cross-functional issues, and supports product development and customer problem resolution.

Design and build frontend experiences and components for the Cloudflare dashboard. Collaborate with design and systems engineers, own code from inception to release, and improve developer experience. Debug, optimize, and identify failure modes in large-scale frontend and distributed systems.

As a Senior AI Compiler Engineer, you will design and build a custom MLIR-based compiler stack for next-gen silicon, optimizing AI models without an OS. Responsibilities include creating MLIR dialects, ensuring accuracy in lowering computational graphs, and maintaining a high-performance compiler codebase.

Leads advanced FPGA and digital design from concept through delivery for mission-critical aerospace and defense systems. Architects and implements FPGA solutions using VHDL, Verilog, SystemVerilog, and major FPGA platforms; performs synthesis, timing analysis, verification, simulation, and hardware-software integration. Supports proposals, technical reviews, lab and flight-test integration, documentation, configuration management, and design optimization. Provides technical leadership and mentorship while managing schedules, budgets, and cross-functional collaboration.

Develop and verify FPGA design environments for electronic warfare systems using SystemVerilog/UVM and/or VHDL. Create constrained-random test plans, self-checking testbenches, reusable verification IP, and coverage-driven test cases. Analyze verification metrics, improve methodologies, execute tasks to schedule, and collaborate with engineers across multiple U.S. locations.

Develop and execute ASIC and IP verification across block and top levels. Build UVM testbenches, TLM models, test plans, and randomized or directed tests; perform RTL debug and coverage closure; and verify hardware with embedded software. The role requires SystemVerilog, UVM, scripting, Linux/Git-based development, and familiarity with interfaces, computer architecture, and relevant semiconductor IP. This is a hybrid, non-remote position in Austin, Texas.

Supports design-for-test development for microprocessor-based SoCs from test requirements through production. Responsibilities include creating and debugging structural test patterns, pre- and post-silicon verification, ATE pattern conversion, built-in self-test implementation, test coverage analysis, and collaboration with Test Engineering, Product Engineering, and fabrication teams.

Design and maintain RTL timing constraints, support physical design and static timing analysis, debug synthesis results, optimize PPA, and contribute to IP, SoC, and micro-architecture development. Perform timing closure, lint, CDC, synthesis, low-power, and quality checks; write tests and automation scripts; collaborate through tape-out; and mentor engineers and interns.

Design and implement low-power microarchitecture, RTL, IP, and SoC components. Develop UPF power intent, perform synthesis, timing closure, lint, CDC, and quality checks, and collaborate with verification, physical design, performance modeling, and test teams. Write tests and automation scripts, debug designs, deliver qualified hardware blocks, and mentor engineers and interns.

Build and own Method’s frontend design craft across its design system, website, dashboard, and embedded product. Develop shader-based Three.js and WebGL experiences, dynamic JSON-driven UI, data visualizations, motion, and React component libraries. Partner with design and engineering leadership to establish visual direction, make implementation tradeoffs, improve frontend quality, reduce contractor reliance, contribute to open source, and eventually help grow the design team.

Designs roadway, highway, complete streets, and multimodal transportation projects from concept through construction. Responsibilities include geometric design, alignments, grading, drainage coordination, plans, specifications, calculations, estimates, technical reports, quality reviews, and construction support. The role coordinates with multidisciplinary teams, clients, contractors, and agencies while ensuring compliance with TxDOT and other applicable standards.

Design and develop CPU logic and RTL based on architecture and microarchitecture specifications. Optimize designs for power, performance, area, and timing; validate functionality through simulation and debugging; document microarchitectural specifications; and collaborate with architecture, verification, physical design, and SoC integration teams.

Lead floorplan design from early architecture through physical implementation for high-performance SoCs/CPUs/GPUs. Collaborate with cross-functional teams to optimize area, power, timing, and interconnect; develop AI-driven workflows and tools; identify technical risks and drive mitigation to meet product goals.

Design, integrate, and sign off synthesizable RTL for ultra-low-power SoC blocks, including compute fabric interconnects, memory interfaces, peripherals, low-power logic, and power-management systems. Own front-end quality through lint, CDC/RDC, LEC, synthesis, timing, and power analysis. Support verification, gate-level debugging, physical-design closure, tapeout, and silicon bring-up while collaborating with architecture, DV, physical design, and firmware teams.

Lead and execute block- and sub-chip physical design including floorplanning, synthesis, placement, CTS, routing, STA, physical verification, formal equivalency, power/IR-drop/EM analysis. Improve flows, automate methodologies, evaluate technology nodes/IP/EDA tools, report status and risks, and support program needs with occasional travel.

Design and verification engineer for Arm’s next-generation network-on-chip interconnect products. Responsibilities include specifying, creating, and debugging SystemVerilog/UVM constrained-random testbenches; verifying multiprocessing microarchitectures, cache coherence, and AMBA protocols; applying software engineering, scripting, and formal verification skills to ensure reliable, high-performance silicon IP.

Owns end-to-end static timing analysis and timing constraints for advanced-node SoCs, from synthesis through final signoff. Responsibilities include timing correlation, path debugging, timing closure, automated and manual ECO generation, constraint validation, and collaboration with frontend, IP, DFT, implementation, and full-chip STA teams. The role also supports methodology improvements, post-silicon bring-up, yield improvement, and production ramp activities.

Own end-to-end SoC timing constraints and static timing analysis from synthesis through signoff. Responsibilities include timing correlation, path debugging, timing closure, automated and manual ECO generation, constraint validation, and collaboration with frontend, IP, DFT, implementation, and full-chip STA teams. The role also supports methodology improvements, post-silicon bring-up, yield improvement, and production ramp activities for advanced-node semiconductor products.

Lead development and delivery of physical design tool flows, methodologies, and sign-off for block, sub-chip, and full-chip levels of Microsoft Next‑Gen AI SoC. Responsibilities include PnR convergence, STA and timing ECOs, PV and FEV sign-off, global clocking, EM/IR analysis, IP collateral validation, design reviews, and mentoring junior engineers.

Leads physical implementation and layout of advanced-node D2D SerDes and analog/mixed-signal IP from floorplanning through tapeout and signoff. Owns matching-critical layout, parasitic control, integration, physical verification, reliability analysis, documentation, and production collateral. Collaborates with circuit, package, signal-integrity, ESD, CAD, foundry, and SoC teams while mentoring contributors and coordinating distributed partners. Develops analog layout automation and methodology improvements using scripting.

Design and develop digital and mixed-signal ASICs and FPGAs using HDL. Build verification methodologies, test benches, test plans, coverage models, and test harnesses. Perform timing, noise, physical design, and signoff analysis; troubleshoot implementation issues; and support lab integration. Collaborate with systems, firmware, architecture, and product engineering teams throughout the ASIC/FPGA lifecycle, while potentially mentoring junior engineers.

Designs and analyzes drainage infrastructure for transportation projects, including storm sewers, culverts, open channels, detention facilities, and roadway drainage networks. Performs hydrologic and hydraulic modeling, engineering calculations, cost estimates, quantity takeoffs, technical reporting, and flood-risk assessments. Coordinates with multidisciplinary teams, clients, and reviewing agencies to ensure compliance with transportation standards and environmental regulations. Supports quality reviews, plan development, agency responses, and construction-related inquiries.