Top Design Engineer Jobs in Austin, TX

As a Senior AI Compiler Engineer, you will design and build a custom MLIR-based compiler stack for next-gen silicon, optimizing AI models without an OS. Responsibilities include creating MLIR dialects, ensuring accuracy in lowering computational graphs, and maintaining a high-performance compiler codebase.

Design and integrate PCIe, CXL, and other IP subsystems for SoCs. Develop micro-architecture specifications and RTL, perform design checks, fix bugs, and collaborate with verification, performance, backend implementation, and project management teams. Support floor planning, constraints, timing closure, and design methodology improvements while guiding team members.

Design and develop FPGA systems through architecture, RTL coding, synthesis, place-and-route, timing closure, simulation, lab testing, product support, and FPGA security. The role requires debugging high-speed interfaces, clock-domain crossings, and digital designs, while supporting testing and mentoring engineers. Preferred experience includes DSP, MATLAB/Simulink, legacy hardware, UVM/SystemVerilog, radar, video/IR processing, stepper motor control, and C/C++.

Designs and develops FPGA systems through architecture, RTL coding, synthesis, place-and-route, timing closure, simulation, lab testing, product support, and FPGA security. The role requires expertise in VHDL or Verilog, FPGA development tools, high-speed interfaces, static timing analysis, clock-domain crossing, debugging, scripting, and revision control. The engineer will support defense electronics programs, collaborate across teams, mentor others, and assist with legacy, DSP, SoC, radar, and low-latency designs.

Own schematic capture and PCB layout for mixed-signal, power, and high-speed digital boards using Altium Designer. Define stack-ups, route power and high-speed interfaces, apply DFM/DFA and EMC/EMI practices, and create manufacturing documentation. Collaborate with electrical, mechanical, thermal, manufacturing, fabricators, and contract manufacturers to deliver production-ready designs. Manage libraries and design rules, support compliance testing, contribute to releases, and mentor junior designers.

The Senior Analog Circuit Design Engineer will design and verify analog circuitry for avionics, collaborate with engineering teams, and perform circuit analysis and troubleshooting.

Responsible for designing, testing, and verifying DC/DC and AC/DC power electronics for military and commercial applications, collaborating with multiple engineering disciplines.

Design, test, and verify DC/DC and AC/DC power electronics for military and commercial aircraft applications, collaborating across multiple disciplines.

Design and validate custom memory circuits for Arm CPUs, GPUs, and SoCs using advanced semiconductor processes. Responsibilities include memory architecture, transistor-level circuit design, layout collaboration, performance-power-area optimization, design margining, physical verification, characterization, front-end verification, release procedures, and quality assurance. The role also involves improving design methodologies and using AI-assisted scripting to increase efficiency and quality.

Design and test power electronics for military and commercial aircraft, conducting research, troubleshooting, and ensuring compliance with specifications.

Lead architecture, design, test, and verification of high-reliability high-speed digital circuit card assemblies for avionics and ground vehicle systems. Provide technical leadership through schematic/layout capture, signal integrity analysis, test plan development, environmental and integration testing, troubleshooting, and cross-functional coordination. Mentor junior engineers and interface with customers, suppliers, and operations to drive design closure and production transition.

Design and build frontend experiences and components for the Cloudflare dashboard. Collaborate with design and systems engineers, own code from inception to release, and improve developer experience. Debug, optimize, and identify failure modes in large-scale frontend and distributed systems.

Lead microarchitecture, RTL development, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink). Translate requirements into synthesizable RTL, collaborate across architecture, verification, firmware, and physical design, analyze traffic and buffering tradeoffs, drive delivery from concept through synthesis and timing closure, mentor engineers, and debug cross-functional issues to meet performance, power, area, and reliability targets.

Collaborate with product designers to implement modular, reusable React components and pixel-perfect UI across desktop and mobile. Build performant CSS-driven interactions, animations, and micro-interactions. Bridge front-end logic with design and maintain high polish across Vetcove's applications.

Lead integration of full-chip or major SoC subsystems, owning top-level flows and cross-domain decisions across DFT, power, timing, and interconnect architecture. Partner with architecture, RTL, physical design, verification, and DFT teams to resolve system tradeoffs. Support organizational growth through hiring and mentoring while remaining hands-on with advanced-node, high-bandwidth, low-power chip designs.

Lead development and delivery of physical design tool flows, methodologies, and sign-off for block, sub-chip, and full-chip levels of Microsoft Next‑Gen AI SoC. Responsibilities include PnR convergence, STA and timing ECOs, PV and FEV sign-off, global clocking, EM/IR analysis, IP collateral validation, design reviews, and mentoring junior engineers.

Own end-to-end electrical hardware development for semiconductor fabrication machines, including clean-sheet PCBA and electrical system design, schematic capture, layout, prototyping, bring-up, testing, integration, documentation, and productionization. Collaborate with software, mechanical, and process teams; investigate design approaches; perform analysis and simulations; and deliver reliable systems autonomously from concept through small-scale production.

Designs and develops custom digital CPU circuits, including memories and caches. Performs floorplanning, schematic entry, simulation, verification, and optimization for power, performance, area, timing, leakage, robustness, and yield. Develops DFT models, memory test tools, and automated design flows. Collaborates with architecture, layout, and cross-functional teams to resolve CPU design issues and characterize memory instances and compilers.

Lead end-to-end PCIe IP integration into complex ASIC and SoC designs, collaborating across architecture, verification, physical design, software, and external IP vendors. Optimize PCIe performance, contribute to IO and interconnect architecture, and lead silicon bring-up, interoperability testing, and debugging across RTL, gate-level, emulation, and post-silicon environments. Mentor engineers and establish PCIe subsystem development practices for high-performance AI and HPC platforms.

Designs and optimizes custom and compiler-based embedded memory solutions for high-performance, low-power CPUs and SoCs. Responsibilities include SRAM, cache, register file, ROM, memory array, bit-cell, and peripheral circuit design; characterization and simulation; critical-path analysis; PPA optimization; automation; methodology development; and cross-functional collaboration with architecture, layout, process, physical design, and validation teams.

Design and architect high-speed 100G+ SerDes signal-processing systems, including equalizers, FEC, filters, modulation, and analog compensation. Develop MATLAB and C/C++ models, simulations, requirements, verification plans, firmware, and lab tests. Collaborate with analog, digital, RTL, firmware, and validation teams to implement and debug ASIC designs. Support communications standards development, customer meetings, technical documentation, and marketing collateral.

Own end-to-end digital design verification for complex SoCs at block, subsystem, and full-chip levels. Develop UVM/SystemVerilog testbenches, verification plans, constrained-random and directed tests, scoreboards, coverage models, and C/C++ SoC validation libraries. Automate regressions and reporting, debug failures, perform root-cause analysis, and collaborate with architecture, design, and software teams. The role requires managing verification milestones, risks, and deliverables through multiple successful tape-outs.

Design Engineering Intern supporting Food and Beverage R&D through concept ideation, product architecture, validation testing, 3D CAD development in SolidWorks, technology and manufacturing-partner research, and progress reporting to engineering leadership.

Design, analyze, prototype, test, and deploy mechanical systems for high-performance computing and custom trading hardware. Create CAD models, production drawings, fixtures, tooling, and technical documentation. Support thermal and structural analysis, fabrication, manufacturing, troubleshooting, and hardware integration while collaborating with electrical, firmware, infrastructure, manufacturing, and vendor teams.

Design end-to-end production machines: mechanisms, end effectors, fixtures, and tooling in Onshape. Prototype with 3D printing and machining, integrate motion, actuators, controls, and vision, then bring machines to production, measure cycle time and reliability, and iterate to improve performance and manufacturability.