Top Design Engineer Jobs in Austin, TX

Design, implement, verify, and optimize FPGA logic (RTL to hardware) for Microchip PolarFire SoCs. Create IP cores, integrate with RISC-V subsystems, build UVM testbenches, run synthesis/place-and-route, perform timing closure and verification, and develop fault- and radiation-tolerant designs for space applications while collaborating with software teams.

Lead FPGA design, implementation, verification readiness, and hardware bring-up for complex server, storage, networking, and AI infrastructure platforms. Provide technical ownership of FPGA architecture and RTL, lead lab debug and validation using lab equipment, resolve cross-domain integration issues, manage schedules and risks, mentor junior engineers, and communicate technical direction to stakeholders.

Develop, integrate, and validate BIOS/UEFI firmware for server/platform products. Support platform bring-up, boot flow validation, subsystem enablement, debug firmware defects, perform root cause analysis, and collaborate with cross-functional teams to ensure release and manufacturing readiness.

Lead BIOS/UEFI firmware development and platform integration across product platforms. Provide technical ownership for firmware features, debug complex issues, optimize performance, ensure validation and manufacturing readiness, collaborate with cross-functional teams, mentor junior engineers, and communicate technical direction and risks to leadership.

Develop next-gen ASICs for space deployment, perform design implementation, collaborate with teams, and resolve timing/congestion issues in chip development.

Develop next-generation silicon for SpaceX's Starlink initiative, performing physical implementation steps, improving methodologies, and collaborating with design teams.

As a CPU microarchitect, you will create specifications, design RTL for functional blocks, and support verification efforts to develop high-performance compute architecture solutions.

Design-for-Test (DFT) engineer responsible for scan chain and compression insertion, MBIST/LBIST, ATPG pattern generation and verification, debugging failures, verifying ATPG testbenches, and collaborating across architecture, design, and customer teams. Work with JTAG/IEEE test standards and Cadence flows to meet test coverage and quality metrics.

The AI Subsystems Physical Design Lead is responsible for timing for subsystems in an AI chip, collaborating with RTL designers, and involved in synthesis, place and route, timing analysis, and power optimization.

The Physical Design Engineer will implement high-performance blocks for CPUs and AI/ML architectures, overseeing the entire flow from synthesis to tapeout and collaborating closely with teams to optimize performance, power, and area.

Lead physical design for block, sub-chip, and full-chip ASIC/SoC implementations. Develop and automate PD flows, evaluate nodes/IP/EDA tools, drive floorplanning through signoff (CTS, placement, routing, STA, verification), optimize power/IR/EM, report risks, and support program needs with occasional travel.

Lead development and delivery of physical design tool flows, methodologies, and sign-off for block, sub-chip, and full-chip levels of Microsoft Next‑Gen AI SoC. Responsibilities include PnR convergence, STA and timing ECOs, PV and FEV sign-off, global clocking, EM/IR analysis, IP collateral validation, design reviews, and mentoring junior engineers.

Partner with product designers to implement pixel-perfect, modular React components and performant CSS for desktop and mobile. Prototype animations and micro-interactions, ensure high-quality UI polish, and bridge front-end logic with design across Vetcove's web platforms.

The Senior/Staff Design Verification Engineer will be responsible for design verification in coherent interconnects. Specific responsibilities are not detailed, but expertise in this area is expected.

Drive physical design for CPUs, GPUs, and SoCs, focusing on netlist aspects, timing convergence, and utilizing EDA tools for high-frequency, low-power designs.

Design and optimize CPU logic and RTL, write and simulate RTL for CPU IP blocks, meet PPA and timing goals, ensure physical design integrity, review verification plans, document microarchitectural specs, and collaborate with SoC customers for integration.

Design and implement mixed-signal IP logic: RTL coding, simulation, and optimization to meet power, performance, area, and timing goals. Collaborate with analog, digital, and physical teams, review and fix RTL verification issues, and support SoC customers for high-quality IP integration.

Design, simulate, and validate advanced I/O and ESD protection circuits. Develop silicon test structures for ESD and latch‑up evaluation, translate silicon data into design rules, release and maintain I/O libraries and models, drive chip‑ and block‑level ESD sign‑off, and lead cross‑team ESD and I/O reliability strategy.

As a Physical Design Engineer, you'll implement complex mixed-signal SoCs, optimizing timing and collaborating within a design team, while also developing design methodologies.

Design end-to-end production machines: mechanisms, end effectors, fixtures, and tooling in Onshape. Prototype with 3D printing and machining, integrate motion, actuators, controls, and vision, then bring machines to production, measure cycle time and reliability, and iterate to improve performance and manufacturability.

Develop wireless communication ICs for IoT applications, design and validate analog/mixed-signal circuits, and lead technical teams in chip design projects.

Design and implement structural RTL for CPU functional blocks from microarchitectural specs. Collaborate with verification and physical design teams to meet performance, timing, power, area, and testability goals. Support test bench and test plan development and assist convergence of blocks to project requirements.

Design and implement TileLink interconnects, cache controllers, protocol bridges and other uncore logic as configurable RTL generators (Chisel/FIRRTL). Improve multi-core coherence, integrate designs into toolchain, perform sandbox verification, collaborate with verification teams, and produce documentation and tests.

Create competitive commercial AV system designs and bid documentation from construction drawings and specifications. Produce shop drawings, pull sheets, and technical documentation; identify scope gaps and risks; collaborate with sales and engineering to deliver technically sound proposals and support engineering work between bids.

Design and optimize ASIC floorplans, collaborate with teams for improvements, and build tools for execution efficiency in chip design.