Top Design Engineer Jobs in Austin, TX

Leads FPGA design verification for electronic warfare systems by architecting SystemVerilog, UVM, OVM, and VHDL testbenches; developing constrained-random test plans; analyzing coverage; creating reusable verification IP; improving methodologies; and mentoring or leading verification teams. The role requires collaboration across sites, schedule and task management, and onsite work.

Produce build-ready electrical designs for islanded behind-the-meter microgrids: single-line and three-line diagrams, wiring schedules, equipment sizing (conductors, OCPD, disconnects, switchgear) across MV/LV/DC, basis-of-design for the Engineer of Record, DC collection layouts, and maintain drawing sets through IFC for procurement and field execution.

Designs and develops mechanical components and assemblies for residential and commercial battery energy storage products. Responsibilities include CAD modeling, manufacturing drawings, tolerance analysis, prototyping, thermal and structural analysis, material selection, DFM, supplier collaboration, electrical integration, testing, validation, and product lifecycle management from concept through production.

Leads semiconductor design verification strategy and execution using UVM/SystemVerilog, constrained-random testing, formal verification, and gate-level simulation. Designs reusable testbenches, develops complex sequences, analyzes coverage, debugs design issues, and oversees verification sign-off. Mentors junior engineers, coordinates with design, architecture, and emulation teams, and manages verification schedules, risks, and priorities.

Lead design verification strategy and execution for customer ASIC projects. Architect reusable UVM/SystemVerilog testbenches, develop constrained-random tests, analyze coverage, perform formal verification and gate-level simulation, debug complex design issues, and provide verification sign-off. Mentor junior engineers, manage verification schedules and risks, and collaborate with design, architecture, emulation, and customers.

Lead verification strategy and architecture for semiconductor ASIC and SoC designs. Build reusable UVM/SystemVerilog testbenches, develop constrained-random tests, perform formal verification and gate-level simulation, analyze coverage, debug complex design issues, and approve verification sign-off. Mentor junior engineers, coordinate with design, architecture, and emulation teams, and manage verification schedules, risks, and priorities.

Leads design verification strategy and architecture for customer ASIC projects. Designs reusable UVM/SystemVerilog testbenches, develops constrained-random tests, manages coverage, performs formal verification and gate-level simulation, and debugs complex design issues. Provides technical leadership through customer interaction, sign-off approval, cross-functional collaboration, project scheduling, risk management, and mentorship of junior engineers.

Develop RTL and microarchitecture for next-generation ASICs used in Starlink space and ground infrastructure. Responsibilities include architectural trade-off analysis, Verilog/SystemVerilog implementation, top-level integration, verification support, timing constraints, synthesis and timing closure, formal checks, and silicon bring-up. The role collaborates with systems, firmware, validation, physical implementation, and product engineering teams.

Lead the design and implementation of debug, trace, and profiling hardware within SiFive's RISC-V ecosystem, focusing on quick market delivery and high performance.

Responsible for physical design and implementation of GPUs and ASICs, including methodology establishment, power/clock distribution, and timing closure.

Implements digital islands within analog chips using ASIC physical design methods including floorplanning, placement, clock tree synthesis, routing, and physical verification. Performs power integrity analysis across multiple voltage domains, optimizing designs for performance, reliability, and manufacturability. Collaborates with analog designers, verification engineers, and global cross-functional teams in mixed-signal environments.

Lead or own verification of fabric interconnect components by defining verification strategies and test plans. Develop UVM-based or formal environments, run and debug simulations, apply random-stimulus and coverage-driven techniques, improve verification efficiency through tools/methodologies, use generative AI in verification tasks, and mentor teammates while collaborating with partner teams to ensure quality and coverage signoff.

Leads integration-level verification of fabric interconnects covering coherency, PCIe/CXL, and configuration traffic. Develops UVM/SystemVerilog environments, test plans, simulations, automation, formal methods, and AI-assisted verification workflows. Collaborates with IP, SoC, and VIP teams, drives coverage and verification closure, improves methodologies, and mentors engineers. Requires a relevant engineering or computer science degree with at least 1–5 years of experience depending on degree level; extensive protocol and verification leadership experience is preferred.

Designs mechanical and electromechanical test fixtures, tooling, and related hardware for optical networking products. Responsibilities include CAD modeling, engineering drawings, BOMs, configuration-controlled documentation, engineering analysis, tolerance studies, fabrication support, assembly, troubleshooting, validation, and deployment. The role collaborates with engineers, technicians, suppliers, and manufacturing partners to deliver reliable, manufacturable solutions throughout the product development lifecycle.

Leads advanced semiconductor package architecture, design, simulation, qualification, and integration from concept through high-volume production. Oversees packaging technologies, layout, materials, assembly flows, reliability testing, OSAT and supplier strategy, yield improvement, and issue resolution. Collaborates across design, manufacturing, quality, reliability, and applications teams while providing technical leadership and mentoring. Requires deep expertise in thermal, mechanical, electrical, and reliability analysis for advanced and power semiconductor packaging.

Own end-to-end physical design for advanced SoCs, from RTL through GDSII and silicon delivery. Lead floorplanning, synthesis, place and route, CTS, routing, timing, power, physical verification, and signoff while meeting PPA targets. Drive methodology, automation, advanced-node implementation, team mentoring, cross-functional collaboration, EDA vendor engagement, post-silicon bring-up, yield improvement, and production ramp activities.

Lead functional verification for Cadence memory controller IP. Develop and enhance UVM-based verification environments, create test plans, validate customer configurations through regression testing, analyze functional and code coverage, support customers using the environment, and ensure designs meet technical and quality requirements.

Designs and develops RF, microwave, and millimeter-wave circuits, modules, subsystems, and systems up to 50 GHz and beyond for aerospace, defense, space, quantum computing, and test applications. Responsibilities include architecture, circuit design, PCB layout support, requirements decomposition, testing, debugging, verification, customer design reviews, compliance documentation, and project planning. Leads small engineering teams and manages deliverables to cost and schedule while ensuring customer and regulatory requirements are met.

Design and develop FPGA systems through architecture, RTL coding, synthesis, place-and-route, timing closure, simulation, lab testing, product support, and FPGA security. The role requires debugging high-speed interfaces, clock-domain crossings, and digital designs, while supporting testing and mentoring engineers. Preferred experience includes DSP, MATLAB/Simulink, legacy hardware, UVM/SystemVerilog, radar, video/IR processing, stepper motor control, and C/C++.

Designs and develops FPGA systems through architecture, RTL coding, synthesis, place-and-route, timing closure, simulation, lab testing, product support, and FPGA security. The role requires expertise in VHDL or Verilog, FPGA development tools, high-speed interfaces, static timing analysis, clock-domain crossing, debugging, scripting, and revision control. The engineer will support defense electronics programs, collaborate across teams, mentor others, and assist with legacy, DSP, SoC, radar, and low-latency designs.

Lead the microarchitecture, SystemVerilog RTL design, integration, optimization, and signoff of complex ASIC and SoC IP for AI inference hardware. Own PPA targets, interfaces, memory integration, verification collaboration, DFT, CDC/RDC, synthesis, timing closure, and post-silicon support. Establish design methodologies, mentor engineers, lead technical reviews, and drive cross-functional architectural decisions.

Design, prototype, build, and validate turbomachinery and vacuum-system equipment for semiconductor fabrication. Responsibilities include mechanical design of frames, components, and assemblies; integrating electromechanical systems; partnering with process, electrical, software, and production teams; sourcing components; and delivering machined and fabricated metal parts into working systems.

Designs, prototypes, validates, and scales specialized semiconductor fabrication equipment and vacuum-system subsystems. Responsibilities include creating mechanical frames, components, and assemblies; integrating mechanical, electrical, optical, and software systems; sourcing components; collaborating with vendors and cross-functional teams; and owning designs through production. The role requires hands-on experience building complex systems, vacuum or fluid-handling expertise, and strong fluid dynamics, thermodynamics, and heat-transfer fundamentals.

Designs and develops mechanical components and systems from concept through production release. Creates 3D CAD models, manufacturing and assembly drawings, bills of material, and layouts using Creo, SolidWorks, Pro/ENGINEER, and AutoCAD. Applies drawing standards, basic GD&T, material and process specifications, DfX practices, and manufacturability optimization. Verifies designs against requirements and may coordinate designers and technical support personnel.

Leads block- and subsystem-level pre-silicon verification and post-silicon validation for custom IP and SoCs. Develops verification strategies, test plans, UVM environments, test content, and coverage closure processes; performs silicon bring-up and debugging. Collaborates with architecture, design, firmware, product engineering, program management, and vendors. Provides technical leadership and mentorship while applying AI-based tools to improve verification efficiency.