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The Principal Design Verification Engineer will lead verification strategies, execute high-performance CPU subsystem verification, and improve methodologies, with a focus on CPU core and coherent interconnect verification.

The Staff Design Verification Engineer will lead verification for a cache-coherent interconnect subsystem, focusing on verification planning, execution, and improving methodologies. Key responsibilities include developing robust verification environments and addressing complex verification problems.

Design and implement CPU power management, reset, and clocking solutions. Collaborate with teams to verify and optimize designs based on RISC-V architecture.

Design interconnect IP, architect TileLink interconnect, enhance performance, integrate into SiFive's framework, perform verification, and maintain documentation.

Lead a performance engineering team to research and develop high-performance processor architectures, defining targets and guiding implementation in RTL, while analyzing performance bottlenecks.

Design and implement debug, trace, and profiling hardware, collaborate with cross-functional teams, and lead improvements in hardware design processes.

Lead the development of SiFive BSPs, creating roadmaps and supporting Yocto-based distributions for various platforms, collaborating with teams and ensuring best open source practices.

The Verification Engineer ensures the accuracy of highly configurable cores and other IPs through state-of-the-art methodologies, test planning, execution, and quality assurance.

Develop and maintain core tools for microprocessor design, including simulation and build tools. Requires systems-level programming and tool validation experience.

Lead the architecture and design of energy-efficient processors, analyze power consumption, and develop models and flows for optimization.