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Design and microarchitect power-management, reset, and clocking subsystems for high-performance CPU and SoC IP. Specify architectures, implement RTL, perform sandbox verification, collaborate with verification, physical implementation, and software teams to meet frequency, area, and power goals.

Design and microarchitect power management, clocking, and reset solutions for RISC-V CPU and SoC IP. Define requirements, implement RTL, collaborate on verification, physical implementation, and software enablement to meet frequency, area, and power goals.

Design and microarchitect power-management, reset, and clocking solutions for high-performance CPU and SoC IP. Develop RTL, spec microarchitecture, run sandbox verification, collaborate with verification, physical implementation, and software teams to optimize frequency, area, and power and drive designs through tapeout.

The Staff Design Verification Engineer drives the verification of cache-coherent interconnect subsystems, focusing on CXL protocols and integration, defining verification plans, and improving overall verification quality through collaboration and mentorship.

The intern will join the Design Verification Infrastructure team to develop and maintain the Verification Platform, enhancing design verification technologies through collaboration and software development in Scala and Python.

Lead a performance engineering team to research, model, and develop high-performance core architectures and microarchitectures. Design experiments, identify HW/SW bottlenecks, and work with design teams to implement and deliver performance targets in RTL and FPGA flows.

Research, model, and develop microarchitecture features for high-performance RISC-V processors. Design and run experiments, identify HW/SW performance bottlenecks, perform workload characterization and reduction, and collaborate with design teams to implement and deliver performance targets in RTL and FPGA prototypes.

Lead verification planning and execution for high-performance out-of-order CPU core blocks. Define verification strategy, develop robust UVM/SystemVerilog environments, write checkers/assertions, drive coverage closure, debug complex microarchitectural issues, and partner with architecture, RTL, performance, and software teams to raise verification quality and provide reusable methodology.

Lead verification planning and execution for high-performance out-of-order CPU core blocks. Define verification strategy, build testbenches, assertions, and coverage models, perform root-cause debug, work with architecture/RTL/performance teams, and drive verification closure and reusable methodology across core generations.

Lead functional verification for high-performance out-of-order CPU cores. Plan and execute block-to-core verification, develop UVM/SystemVerilog testbenches, write coverage and assertions, create constrained-random and directed tests, debug failures, collaborate with architects and RTL teams, and contribute reusable DV methodology and infrastructure to achieve signoff-quality verification.