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The role involves CPU core verification for out-of-order RISC-V CPUs, requiring in-depth microarchitecture knowledge and development/debugging of functional verification models.

Drive top-level implementation of complex AI and CPU SoC designs, ensuring design closure and optimizing chip-level implementations for power, performance, and area.

The Design for Test Engineer will implement DFT features in RTL, analyze test coverage, and support silicon bring-up for advanced AI/ML architectures.

Develop and optimize distributed software systems for AI and HPC clusters, focusing on inter-node communication and scalable architectures.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

Lead the development of AI compiler tools, enhance performance analysis, collaborate with hardware teams, and mentor engineers to improve compiler tooling.

Develop and maintain infrastructure platforms for AI services, build APIs, manage Kubernetes clusters, and automate workflows using CI/CD practices.

As a Staff Engineer, you will lead the technical efforts in CPU verification, emulation, and debugging, optimizing the emulation infrastructure and workflow for high-performance CPUs, collaborating with teams to ensure fast and effective product development.