Top Tech Jobs & Startup Jobs in Austin, TX

Shape and evaluate next-generation high-performance RISC-V CPUs using performance modeling and simulation. Build and run architectural models (Gem5/SST/SimpleScalar), analyze pipelines, caches, branch prediction, and memory hierarchies, implement modeling and analysis tools in C++/Python, and collaborate with CPU architects to optimize AI/HPC workload performance. Hybrid role based in Santa Clara or Austin.

Leads the strategy, architecture, implementation, and evolution of Finance Systems. Owns ERP and financial systems roadmaps, finance process transformation, integrations, data architecture, automation, AI applications, controls, and cross-functional technology programs. Builds a scalable, data-driven Finance technology organization supporting global growth, accounting, tax, treasury, supply chain, manufacturing, reporting, and planning.

Own global compensation cycles, review processes, offer governance, and compensation data. Run end-to-end benchmarking, equity budgeting, and dilution analysis. Build SQL-based analyses and Tableau dashboards with measurable adoption. Serve as the go-to partner for HRBPs, managers, and recruiters to translate data into actionable compensation decisions.

Responsible for physical design of high-performance CPUs and AI/ML architectures, including implementation from synthesis to tapeout, and collaborating with front-end teams.

Own end-to-end physical implementation of AI accelerator and RISC-V IP blocks from synthesis through PnR, timing closure, and GDSII signoff. Drive PPA outcomes, collaborate with RTL owners, build floorplans, power grids, pin placement and clocking strategies, and deliver LEF/DEF, timing and power models, GDS, and signoff reports for tapeouts on advanced nodes.

As a Full-Chip Physical Design Verification Engineer, you will ensure manufacturable silicon by driving full-chip signoff, leading physical verification closure, and collaborating with various teams to achieve successful tapeouts.

The AI Subsystems Physical Design Lead is responsible for timing for subsystems in an AI chip, collaborating with RTL designers, and involved in synthesis, place and route, timing analysis, and power optimization.

The Physical Design Engineer will implement high-performance blocks for CPUs and AI/ML architectures, overseeing the entire flow from synthesis to tapeout and collaborating closely with teams to optimize performance, power, and area.

Lead go-to-market positioning and messaging for Tenstorrent's AI hardware and software stack. Develop application- and vertical-specific value propositions, technical collateral (whitepapers, benchmarks, demos, sales decks), and field enablement. Partner closely with product, engineering, sales, and marketing to align roadmap, launches, and customer solutions. Translate technical capabilities into business value for enterprise, cloud, and regulated markets while gathering customer and competitive insights to inform strategy.

Lead go-to-market positioning and solution strategy for Tenstorrent's AI hardware and software stack. Develop application- and vertical-specific value propositions, technical collateral (whitepapers, decks, benchmarks, demos), and customer stories. Partner with product, engineering, sales, and marketing to align roadmaps, launches, and field enablement, translating deep technical capability into clear customer outcomes.