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The Staff Technical Program Manager will lead semiconductor physical design projects, managing complex schedules and facilitating communication between teams and clients within AI/ML and CPU initiatives.

The STA Methodology Engineer will lead the optimization of timing methodologies and automation, collaborating across teams to address advanced-node design challenges.

Design, develop, and optimize GCC and LLVM compilers for RISC-V and AI architectures, collaborating across hardware and software teams to enhance performance.

Design and simulate high-speed interconnects, collaborate with teams on specifications, troubleshoot issues, and support post-silicon bring-up and validation.

Lead cross-functional product development for AI processors and systems from concept to delivery. Drive schedules, risks, dependencies, and stakeholder alignment across hardware, software, firmware, validation, manufacturing, and suppliers. Communicate technical status to executives and coordinate structured product development processes in a hybrid, collaborative environment.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.

The Timing Engineer will perform static timing analysis, optimizing paths and constraints to ensure chip performance while collaborating with various engineering teams.

Lead EM and IR-drop simulations ensuring robust power delivery and signal integrity for high-performance ICs. Collaborate with teams on power grid strategies and support EMIR sign-off across chip hierarchy.

Define architecture and micro-architecture specs for memory and I/O chiplets, evaluate next-generation memory technologies, develop performance and power modeling infrastructure, and collaborate with SoC, verification, physical design, packaging, systems teams and external partners to enable high-throughput, low-latency memory architectures.

Lead hardware-software co-design to enable AI/HPC and agentic AI stacks on RISC-V CPUs. Integrate and optimize low-level kernel infrastructure, runtimes, distributed execution, memory systems, and developer tools, collaborating with architects, compiler engineers, and kernel developers to meet performance targets.