Top Tech Jobs & Startup Jobs in Austin, TX

The Sr. Engineer will work on CPU design, focusing on RTL implementation, collaborating with micro-architects, and optimizing performance, power, and area.

As a SOC Emulation Engineer, you'll support hardware emulation infrastructure, integrating hardware transactors and developing Python-based test frameworks while providing technical support across chip projects.

Build and operate AI inference deployments, write production code, debug full inference stack, collaborate with customers and engineering, and drive performance/observability improvements using Kubernetes, Helm, and LLM serving tools.

Develop, deploy, and own RTL-to-GDSII physical design methodology and CAD flows for IP delivery. Automate PPA exploration, document flows, partner with design teams and EDA vendors, qualify new nodes/PDKs and EDA releases, and apply ML/LLMs where they improve flow optimization and scalability.

Design and validate high-bandwidth interconnects for AI clusters across copper and optical media. Define architectures, perform link and channel budget analysis, lead qualification and reliability testing, develop validation plans for transceivers and cables up to 1.6T, and coordinate with suppliers and manufacturing.

The Staff Technical Program Manager will lead semiconductor physical design projects, managing complex schedules and facilitating communication between teams and clients within AI/ML and CPU initiatives.

Design, develop, and optimize GCC and LLVM compilers for RISC-V and AI architectures, collaborating across hardware and software teams to enhance performance.

Design and simulate high-speed interconnects, collaborate with teams on specifications, troubleshoot issues, and support post-silicon bring-up and validation.

Design Verification Engineer responsible for verifying Tensix IP, building reusable SystemVerilog/Python testbenches and DV infrastructure, developing constrained-random and directed tests, closing coverage, debugging RTL/testbench/workload issues, and integrating CI/CD, simulation/emulation, and containerized regression systems. Collaborates with design, firmware, compiler, and architecture teams.

Lead the development of CPU core-level test generators for RISC-V processors, overseeing validation strategies and guiding a small team while staying hands-on with implementation.