Top Tech Jobs & Startup Jobs in Austin, TX

Design, implement, and maintain TT-Fabric, a low-level high-performance networking library for large-scale AI clusters. Build scalable communication protocols, optimize synchronization and data movement for thousands of processors, integrate APIs with AI and hardware teams, and help define the distributed systems architecture to maximize hardware performance.

Develop and optimize distributed software systems for AI and HPC clusters, focusing on inter-node communication and scalable architectures.

Lead CPU core-level testbench development and verification for high-performance out-of-order RISC-V CPUs, involving hands-on infrastructure development and debugging using AI methodologies.

Lead post-silicon power characterization and correlation for semiconductor products, develop measurement strategies, and improve power architectures to meet specifications.

Lead customer engagements for RISC-V CPU server and machine learning processor projects, coordinating with engineering teams and managing technical program requirements.

The Physical Design Engineer will lead efforts in solving physical design challenges, improve RTL-to-GDS methodologies, and integrate AI/ML solutions into CAD flows, focusing on performance and runtime improvements.

The Sr. Engineer will work on CPU design, focusing on RTL implementation, collaborating with micro-architects, and optimizing performance, power, and area.

Build and operate AI inference deployments, write production code, debug full inference stack, collaborate with customers and engineering, and drive performance/observability improvements using Kubernetes, Helm, and LLM serving tools.

Develop, deploy, and own RTL-to-GDSII physical design methodology and CAD flows for IP delivery. Automate PPA exploration, document flows, partner with design teams and EDA vendors, qualify new nodes/PDKs and EDA releases, and apply ML/LLMs where they improve flow optimization and scalability.

Design and validate high-bandwidth interconnects for AI clusters across copper and optical media. Define architectures, perform link and channel budget analysis, lead qualification and reliability testing, develop validation plans for transceivers and cables up to 1.6T, and coordinate with suppliers and manufacturing.