Top Tech Jobs & Startup Jobs in Austin, TX

Early-career, customer-facing program preparing new graduates to support customers through evaluation, design, demos, and deployment of NXP semiconductor solutions. Collaborate with sales, product, and applications teams to translate requirements into system-level solutions, lead customer engagements, and develop technical depth toward TSE or FAE roles.

Design and implement cost-effective test methods for IP on advanced-node SOC microprocessors. Support characterization, qualification, production test, and debug; develop diagnostic programs; collaborate with design and verification teams pre-tapeout; understand high-speed ATE hardware and semiconductor manufacturing test economics.

Lead export control and sanctions compliance for the AMEC region, driving strategy implementation, regulatory adherence, and operational efficiency while engaging stakeholders and optimizing processes.

Design and deliver digital IP (RTL) for SoC components using Verilog/SystemVerilog; plan documentation and schedules; collaborate with verification to achieve full coverage; perform quality checks (Lint, CDC, STA); track metrics and support SoC integration, validation, and field issue resolution.

Develop and execute IP verification plans using SystemVerilog/UVM and SVA. Create random and directed tests, implement monitors/drivers/checkers, debug failures, collect/analyze coverage, and perform assertion-based formal verification. Maintain verification environments, scripts, and Makefiles while collaborating with architecture, design, and verification teams to ensure IP quality.

Lead development and execution of verification plans and testbenches for MCU/MPU digital IP. Build UVM/OVM components, constrained-random stimulus, SVA assertions, formal checks, coverage models, and debug failures. Provide technical leadership, mentor engineers, and collaborate with global SoC/IP teams to drive best practices.

Lead development and execution of verification plans and testbenches for digital IP. Create UVM/OVM testbench components, constrained-random and directed tests, SVA assertions, functional coverage models, and apply formal methods. Debug RTL, analyze coverage results, mentor engineers, and collaborate with global SoC/IP teams to drive zero-defect quality and productivity improvements.

Design and verify DFT features at subsystem and top levels: insert and verify MBIST, analyze/fix scan DRCs, run ATPG coverage and pattern generation, insert TAP/IO/test pinmux, perform power-aware RTL/GLS simulations, and support pattern bring-up with product and test teams.

Define and implement IP/subsystem-level verification strategy. Write SystemVerilog/UVM testbenches, assertions, random and directed tests. Perform simulation, debug failures, collect/analyze coverage, and run assertion-based formal verification. Develop verification infrastructure, scripts, and use AI to augment productivity.

Lead verification for MCU/MPU digital IP: define and execute verification plans, build UVM-based testbenches and SVA, develop constrained-random and directed tests, apply formal methods, debug failures, analyze RTL and coverage, and mentor a small team to ensure zero-defect delivery.