Top Tech Jobs & Startup Jobs in Austin, TX

Provides technical leadership for digital IP verification, including verification planning, UVM testbench development, constrained-random and directed testing, coverage analysis, assertions, formal verification, debugging, and root-cause analysis. Mentors engineers and promotes zero-defect verification practices for automotive and microcontroller semiconductor products.

Advise senior leadership on U.S. regulatory matters, especially export controls and regulations affecting cross-border capital flows and technology operations. Identify and mitigate regulatory risks across the semiconductor landscape, interpret emerging frameworks, collaborate with global teams and U.S. regulators, and support business objectives involving EAR, ITAR, OFAC, CFIUS, government contracting, outbound investment, and connected vehicle rules.

Lead the Americas Central Region sales team to hit quarterly and annual targets by building high-performance quota-carrying teams, developing territory and channel strategies, enabling executive customer relationships, coordinating technical resources, and collaborating with peer leadership to drive design wins, funnel growth, and revenue. Manage escalations, recruiting, and team performance to meet NXP financial goals.

Lead AI/ML-driven automation for ASIC and SoC design implementation. Explore and prototype generative AI, reinforcement learning, graph neural networks, and convolutional network solutions for VLSI optimization, focusing on power, performance, area, and quality. Collaborate with academic researchers and cross-functional architecture, design, verification, and implementation teams to evaluate methodologies, develop CAD tools, and pilot automation across advanced automotive processor and microcontroller designs.

Design and specify hardware security architectures and requirements, perform attack modeling and pre-silicon vulnerability analysis, review RTL and firmware implementations, advise/train teams, support certification and evaluators, interface with customers and product teams, and perform root cause analysis of security defects.

Define and drive SoC hardware security architecture and requirements, including HSM, secure boot/Root of Trust, cryptographic IP, and secure key provisioning. Lead threat modeling, vulnerability analysis, and HW/SW co-design to embed security across RTL, DFT, physical design, and firmware. Ensure compliance with cybersecurity and functional safety standards, collaborate cross-functionally, and provide technical leadership for system-level security validation.

Characterize and model next-generation non-volatile memory (NVM) technologies, perform statistical reliability analysis, set qualification requirements, collaborate with foundries and product teams to ensure high-volume production reliability, and communicate results to internal and external stakeholders.

Design and verify DFT features at subsystem and top levels: insert and verify MBIST, analyze/fix scan DRCs, run ATPG coverage and pattern generation, insert TAP/IO/test pinmux, perform power-aware RTL/GLS simulations, and support pattern bring-up with product and test teams.

Lead development and execution of verification plans and testbenches for digital IP. Create UVM/OVM testbench components, constrained-random and directed tests, SVA assertions, functional coverage models, and apply formal methods. Debug RTL, analyze coverage results, mentor engineers, and collaborate with global SoC/IP teams to drive zero-defect quality and productivity improvements.

Lead verification for MCU/MPU digital IP: define and execute verification plans, build UVM-based testbenches and SVA, develop constrained-random and directed tests, apply formal methods, debug failures, analyze RTL and coverage, and mentor a small team to ensure zero-defect delivery.