Top Tech Jobs & Startup Jobs in Austin, TX

The Director, Global HR Business Partner engages with senior leaders to align people strategies with business objectives, influencing decisions through data and strategic insights while ensuring innovative talent management practices.

Lead export control and sanctions compliance for the AMEC region, driving strategy implementation, regulatory adherence, and operational efficiency while engaging stakeholders and optimizing processes.

Design and verify DFT features at subsystem and top levels: insert and verify MBIST, analyze/fix scan DRCs, run ATPG coverage and pattern generation, insert TAP/IO/test pinmux, perform power-aware RTL/GLS simulations, and support pattern bring-up with product and test teams.

Design and deliver digital IP (RTL) for SoC components using Verilog/SystemVerilog; plan documentation and schedules; collaborate with verification to achieve full coverage; perform quality checks (Lint, CDC, STA); track metrics and support SoC integration, validation, and field issue resolution.

Lead development and execution of verification plans and testbenches for digital IP. Create UVM/OVM testbench components, constrained-random and directed tests, SVA assertions, functional coverage models, and apply formal methods. Debug RTL, analyze coverage results, mentor engineers, and collaborate with global SoC/IP teams to drive zero-defect quality and productivity improvements.

Lead development and execution of verification plans and testbenches for MCU/MPU digital IP. Build UVM/OVM components, constrained-random stimulus, SVA assertions, formal checks, coverage models, and debug failures. Provide technical leadership, mentor engineers, and collaborate with global SoC/IP teams to drive best practices.

Lead verification for MCU/MPU digital IP: define and execute verification plans, build UVM-based testbenches and SVA, develop constrained-random and directed tests, apply formal methods, debug failures, analyze RTL and coverage, and mentor a small team to ensure zero-defect delivery.

Define and implement IP/subsystem-level verification strategy. Write SystemVerilog/UVM testbenches, assertions, random and directed tests. Perform simulation, debug failures, collect/analyze coverage, and run assertion-based formal verification. Develop verification infrastructure, scripts, and use AI to augment productivity.

Develop and prototype AI/ML-driven automation for ASIC/SoC design and implementation. Collaborate with academia and cross-functional NXP teams to apply GenAI, RL, GNNs, and CNNs to VLSI CAD flows, pilot solutions on real designs, and improve power, performance, area, and quality.

Define roadmap and product specifications for protocol bridges and connectivity hubs. Engage customers, perform competitive analysis, coordinate cross-functional teams to develop demos, reference designs, and documentation. Provide application support, technical training, and contribute to standards while overseeing development of demonstration boards and securing design-ins.