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The role involves developing verification strategies for mixed-signal designs, creating behavioral models, and debugging testbenches using UVM and SystemVerilog for high-speed communication technology.

Responsible for end-to-end verification of RTL designs, leading test bench architecture, mentoring engineers, and ensuring full functionality through detailed coverage analysis.

The DFT Engineer will define and implement DFT methodologies for complex digital chips, debug DFT features, and validate silicon tests.