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12 Hours AgoSaved
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Remote
United States
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170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
Lead the design and implementation of digital subsystems for state-of-the-art wireless SoCs for satellites, optimizing for power, performance, and area.
Top Skills: C++MatlabPythonSystemverilogVerilog
14 Hours AgoSaved
Easy Apply
Remote
United States
Easy Apply
170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
Design and develop mixed-signal ICs and architectures for satellite systems, collaborating with cross-functional teams to optimize performance and maintain documentation.
Top Skills: Cadence VirtuosoFinfet TechnologyHigh-Speed Data Converter (Adc/Dac)MatlabPhase-Locked Loop (Pll)SpectreVerilog-AVerilog-Ams
14 Hours AgoSaved
Easy Apply
Remote
United States
Easy Apply
190K-285K Annually
Expert/Leader
190K-285K Annually
Expert/Leader
Defense • Manufacturing
Lead the design of mixed-signal ICs focusing on ADC/DAC and PLL, ensuring integration and compliance for satellite communication systems while mentoring team members.
Top Skills: Cadence VirtuosoEda ToolsFinfet TechnologyMatlabSpectreVerilog-AVerilog-Ams
14 Hours AgoSaved
Easy Apply
Remote
United States
Easy Apply
190K-285K Annually
Senior level
190K-285K Annually
Senior level
Defense • Manufacturing
The Principal Digital ASIC Design Engineer will lead development of digital subsystems for SoCs, optimizing designs, collaborating on DSP implementations, and mentoring team members, ultimately contributing to spacecraft technology.
Top Skills: C++CadenceDsp SystemsEda ToolsMatlabPythonRtl DesignSiemensStatic Timing AnalysisSynopsysSynthesisSystemverilogVerilog
14 Hours AgoSaved
Easy Apply
Remote
United States
Easy Apply
200K-300K Annually
Senior level
200K-300K Annually
Senior level
Defense • Manufacturing
Lead a team of digital design engineers, manage ASIC design schedules, develop RTL for digital subsystems, and conduct verification and validation activities.
Top Skills: C++CadenceMatlabPythonSiemens ToolsSynopsysSystemverilogVerilog
14 Hours AgoSaved
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Remote
United States
Easy Apply
130K-200K Annually
Junior
130K-200K Annually
Junior
Defense • Manufacturing
Design and implement digital subsystems for advanced wireless SoCs; collaborate on mixed-signal SoCs tailored for satellite communications.
Top Skills: C++MatlabPythonSystemverilogVerilog
Reposted 5 Days AgoSaved
Easy Apply
Remote
United States
Easy Apply
160K-220K Annually
Senior level
160K-220K Annually
Senior level
Defense • Manufacturing
As a Senior GNC Engineer, you will lead spacecraft GNC architecture development, implement control algorithms, conduct simulations, and support flight readiness for innovative satellite missions.
Top Skills: C/C++JuliaMatlabPythonRust
Reposted 7 Days AgoSaved
Easy Apply
Remote
United States
Easy Apply
190K-250K Annually
Senior level
190K-250K Annually
Senior level
Defense • Manufacturing
As a Principal GNC Engineer, you will drive spacecraft GNC architecture, execute verification plans, support launch operations, and develop simulation tools while mentoring other engineers.
Top Skills: C/C++JuliaMatlabPython
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