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Top Tech Jobs & Startup Jobs in Austin, TX

Reposted 6 Hours AgoSaved
Remote
United States
120K-180K Annually
Senior level
120K-180K Annually
Senior level
Defense • Manufacturing
As a Senior RFIC Layout Designer, you will implement RF and mixed-signal IC layouts for satellite communication systems, focusing on layout execution and integration with cross-functional teams. Duties include ensuring layout quality, collaborating with design teams, and driving chip signoff processes.
Top Skills: CadDrcEmErcEsdFinfetIrLvsMixed-Signal IcRfic
2 Days AgoSaved
Remote
United States
160K-235K Annually
Senior level
160K-235K Annually
Senior level
Defense • Manufacturing
As a Senior GNC Engineer, you will design and implement orbital guidance, control systems, and estimation algorithms for spacecraft, supporting multiple missions.
Top Skills: C/C++JuliaMatlabPythonRust
Reposted 3 Days AgoSaved
Remote
United States
190K-260K Annually
Senior level
190K-260K Annually
Senior level
Defense • Manufacturing
The Principal GNC Engineer will drive spacecraft GNC architecture, perform verification and validation, develop tools and algorithms, and support launch operations, while mentoring engineers.
Top Skills: C/C++JuliaMatlabPython
Reposted 3 Days AgoSaved
Remote
United States
190K-285K Annually
Expert/Leader
190K-285K Annually
Expert/Leader
Defense • Manufacturing
Lead architecture and development of low-level embedded firmware for mixed-signal and digital SoCs, ensuring first-silicon success and robust firmware foundations.
Top Skills: CC++Rtos
6 Days AgoSaved
Remote
United States
170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
Develop and enhance low-level embedded firmware for high-performance mixed-signal and digital SoCs. Collaborate with various engineering teams to ensure reliable firmware foundations for next-generation products.
Top Skills: ArmCC++JtagRisc-V
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10 Days AgoSaved
Remote
United States
190K-280K Annually
Senior level
190K-280K Annually
Senior level
Defense • Manufacturing
Lead the development of SoCs for satellites, manage physical design partners, ensure timing closure, and support design integration.
Top Skills: CadenceEdaGdsiiRtlSiemensSynopsys
10 Days AgoSaved
Remote
United States
130K-200K Annually
Mid level
130K-200K Annually
Mid level
Defense • Manufacturing
The ASIC Physical Design Engineer will implement advanced SoCs for satellites, executing design flows, optimizing performance, and collaborating across teams for integration and testing activities.
Top Skills: Cadence InnovusFusion CompilerSynopsys Icc2
10 Days AgoSaved
Remote
United States
180K-260K Annually
Senior level
180K-260K Annually
Senior level
Defense • Manufacturing
The engineer will define and implement ASIC package architecture, focusing on FC-BGA and MCM solutions, collaborating on package design and ensuring successful production of high-performance ASICs.
Top Skills: AdsAsic DesignFc-BgaHfssMcmSi Wave
10 Days AgoSaved
Remote
United States
200K-280K Annually
Senior level
200K-280K Annually
Senior level
Defense • Manufacturing
The role involves leading ASIC package design for FC-BGA and MCM solutions, ensuring high-performance mixed-signal/digital SoCs succeed from architecture to production. Responsibilities include trade studies, design standards, and vendor collaboration.
Top Skills: AdsFc-BgaHfssMcmSiwave
10 Days AgoSaved
Remote
United States
130K-200K Annually
Junior
130K-200K Annually
Junior
Defense • Manufacturing
As an ASIC Synthesis and Timing Engineer, you'll implement complex SoCs for satellite systems, develop timing constraints, optimize PPA, and ensure design integration with partners.
Top Skills: Asic DesignCadenceRtl-To-Gdsii FlowsSiemensSynopsys
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