Own and scale hardware-design and software build/CI infrastructure: manage PDKs, EDA tools and license servers, integrate third-party IP, maintain reproducible ASIC flows and CAD environments, run CI pipelines, manage compute and containerized dev environments, and support compiler/runtime teams to improve tooling uptime and onboarding.

Lead and scale verification and emulation organization: define end-to-end DV strategy, drive UVM-based methodology and emulation for early software enablement, deliver pre-silicon platforms, manage emulation lab and vendor relationships, hire and mentor a team, and ensure tapeout verification closure.

The Lead STA Engineer will develop timing flows and methodologies for advanced processor technologies, ensuring timing convergence and contributing to the design and production process.