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Lead the microarchitecture, SystemVerilog RTL design, integration, optimization, and signoff of complex ASIC and SoC IP for AI inference hardware. Own PPA targets, interfaces, memory integration, verification collaboration, DFT, CDC/RDC, synthesis, timing closure, and post-silicon support. Establish design methodologies, mentor engineers, lead technical reviews, and drive cross-functional architectural decisions.

Lead the architecture, design, verification, physical implementation, tape-out, validation, and production ramp of high-performance AI inference ASICs. Drive PPA optimization, memory subsystem design, hardware/software co-design, and relationships with foundries, IP vendors, and EDA providers. Recruit and mentor the ASIC team while shaping the company’s silicon roadmap and execution methodology.

Owns synthesis methodology, timing closure, constraint development, QoR optimization, and implementation readiness for advanced AI accelerator ASICs. The role transforms RTL into implementation-ready netlists, leads physical-aware optimization and timing budgeting, collaborates across architecture, verification, DFT, and backend teams, and provides technical leadership to external implementation partners. Responsibilities also include developing Tcl and Python automation and applying AI to improve timing analysis, regression, debugging, and engineering workflows.

Develop and lead verification strategies for AI inference ASICs, including SystemVerilog UVM environments, simulation testbenches, directed and constrained-random testing, coverage closure, debugging, and root-cause analysis. Collaborate with design, architecture, software, FPGA, and emulation teams across pre-silicon and post-silicon validation. Manage verification schedules, deliverables, and risk mitigation while helping ensure functional correctness and performance.

Lead ASIC/SoC IP and subsystem development from microarchitecture through RTL signoff. Design parameterized SystemVerilog RTL, own PPA targets, and lead lint, CDC/RDC, DFT, synthesis, and timing activities. Architect interfaces, DMA, coherency, and HBM/DDR integration while collaborating with architecture, verification, and physical design teams. Improve design methodologies, mentor engineers, lead reviews, support post-silicon debug, and contribute automation flows.

Lead pre-silicon emulation strategy for a next-generation AI inference ASIC using Cadence Palladium. Architect multi-rack models, enable software left-shift via hybrid emulation, verify high-speed interfaces and memory hierarchies, perform power/performance analysis, and collaborate with RTL, DV, software teams and Cadence R&D to ensure silicon readiness.

Define multi-generation hardware/software architectures for AI inference silicon, including boot, memory, DMA, scheduling, security, telemetry, and host/device interfaces. Integrate firmware, Linux, runtimes, simulation, and developer tooling; lead architecture reviews; resolve cross-team technical issues; prototype high-risk interfaces; and mentor senior engineers. The role requires deep systems expertise, strong C or C++ skills, and architecture-level ownership across pre-silicon, silicon bring-up, and production software.

Build simulation and modeling infrastructure for AI inference accelerators before silicon availability. Develop analytical performance models, functional and timing simulators, virtual platforms, and software integrations. Validate functionality and performance against reference implementations and hardware, improve simulator speed and usability, and create automated regression coverage. Collaborate with hardware, compiler, firmware, runtime, performance, and test engineers to support architecture exploration and realistic software workloads.

Owns AI-assisted engineering across accelerator software teams, embedding agentic workflows into coding, debugging, triage, testing, documentation, CI, and silicon-debug processes. Builds shared agent tooling, maintains evaluations, measures productivity gains, and establishes standards for reliable AI-native development. Requires expert experience with Codex, Claude Code, LLM APIs, evaluations, and adopted developer tooling, plus strong systems or infrastructure credibility.

The Senior Software Engineer will develop high-performance software for executing open-source LLMs on custom hardware, focusing on optimizations and efficient libraries primarily in C++.