Top Tech Jobs & Startup Jobs in Austin, TX

Lead full-chip physical design: floorplanning, partitioning, clock and power planning, place-and-route, STA, power integrity, signoff, tool/flow improvements, collaboration across RTL, DFT, EDA vendors, foundry and post-silicon teams, and apply AI tools to improve productivity.

Lead CDC/RDC methodology for ASIC subsystems: design and implement CDC-aware RTL, define CDC check flows and SDC constraints, perform static glitch and gate-level analysis, review/approve constraints and waivers, and collaborate with CAD to productionize robust, reusable silicon designs.

Lead ASIC implementation with a focus on Design-for-Test (DFT): define DFT architecture, coordinate with RTL and physical design teams, drive ATPG and EDA tool use, own test infrastructure and post-silicon validation, collaborate on timing closure and electrical planning, and develop reusable DFT IP and verification flows.

Lead and grow an SRE team operating the ThousandEyes FedRAMP US GovCloud platform. Own FedRAMP-compliant infrastructure strategy, continuous monitoring, logging, and auditing. Partner with product, dev, and security teams to ensure availability, automation, vulnerability management, and compliance with FedRAMP controls.

Lead DFT implementation for high-performance ASICs, collaborating with RTL and physical design teams to define and integrate test logic, develop DFT IP, enable ATPG/ATE flows, perform test-timing analysis, and drive post-silicon validation and debug across the full implementation lifecycle.

Lead end-to-end semiconductor supply chain transformation by translating strategy into roadmaps, designing optimized processes, enabling Oracle ERP transformations, using analytics and AI, mentoring architects, and establishing governance to drive measurable business outcomes.

Lead product strategy for AI/ML features in ThousandEyes, working with engineering and research to design, validate, and ship AI-native, agentic capabilities on network telemetry data. Translate customer problems into model-driven solutions, optimize model/user trade-offs, and move research into reliable production features.

Lead go-to-market strategy for AI-powered networking use cases across Cisco Networking. Curate and prioritize use cases, synthesize cross-portfolio intelligence, define GTM and messaging, engage customers and analysts, align stakeholders, and drive adoption from early availability to general availability.

Lead verification of next-generation 100G–1.6T coherent optical ASICs: create test plans and benches, apply advanced verification techniques, supervise execution, drive chip-level tradeoffs, review coverage and code, mentor engineers, and improve verification processes.

Lead full-chip physical design: floorplanning, partitioning, pin/bump assignment, clock planning, power-grid planning, place-and-route, STA, power integrity, physical verification and equivalence checks. Improve EDA flows, collaborate with RTL/DFT/package/foundry/IP teams, use UPF for low-power design, and apply Python and AI tools to boost productivity.