Top Tech Jobs & Startup Jobs in Austin, TX

Lead and execute block- and sub-chip physical design including floorplanning, synthesis, placement, CTS, routing, STA, physical verification, formal equivalency, power/IR-drop/EM analysis. Improve flows, automate methodologies, evaluate technology nodes/IP/EDA tools, report status and risks, and support program needs with occasional travel.

Leads advanced semiconductor package technology selection, design, qualification, manufacturing bring-up, supplier management, and reliability for Microsoft Azure silicon. Responsibilities include chiplet-based 2.5D/3D package development, substrate and assembly design, test vehicle definition, FMEA, EDA requirements, supplier assessments, package characterization, and cross-functional architecture decisions. The role requires extensive semiconductor packaging, manufacturing, reliability, simulation, and supplier-management expertise.

Own SoC implementation and integration strategies for Microsoft silicon. Integrate functional blocks, assess area, power, and performance, support RTL quality, write tests, debug IP and SoC functionality, and lead gate-level simulation. Perform lint, CDC, RDC, low-power, synthesis, timing, and power checks while collaborating with design and verification teams to deliver high-quality ASIC and SoC products.

Lead Microsoft’s commercial cloud demand planning organization for Azure Standard Storage and XArchive. Oversee forecasting, capacity and hardware demand planning, rack deployment, supply optimization, decommissioning, migrations, and capital expenditure planning across 24–36-month horizons. Build and coach technical program management and planning teams, drive data-driven decisions, and collaborate with Engineering, Finance, Hardware, Data Centers, and Supply Chain stakeholders to optimize availability, cost, margins, and customer experience.

Leads power and performance strategy for next-generation Azure AI compute platforms. The role drives silicon and platform architecture, workload characterization, benchmarking, power optimization, performance tuning, and efficiency improvements. It partners across hardware, firmware, operating systems, manufacturing, validation, and customer engineering teams, while mentoring engineers and influencing silicon and platform roadmaps. The position requires expertise in compute architectures, AI workloads, power management, thermal systems, datacenter infrastructure, and cross-functional technical leadership.

Validate and verify DPU ASIC/SoC silicon across pre- and post-silicon stages. Own verification strategies, develop UVM/C testbenches, run and debug simulations, apply coverage and random-stimulus techniques, and collaborate with architecture and partner teams to meet test plan and performance goals.

Own the multi-year sourcing vision and category strategies for Azure spares hardware. Lead supplier relationships, strategic negotiations, capacity planning, cost optimization, risk mitigation, and executive governance. Develop sourcing frameworks covering make-or-buy, multi-sourcing, lifecycle transitions, warranty, repair, reuse, and total cost of ownership. Transform sourcing processes through scalable data, analytics, and AI-enabled tools while influencing Engineering, Quality, Finance, Planning, and senior supplier leadership.

Lead development and delivery of physical design tool flows, methodologies, and sign-off for block, sub-chip, and full-chip levels of Microsoft Next‑Gen AI SoC. Responsibilities include PnR convergence, STA and timing ECOs, PV and FEV sign-off, global clocking, EM/IR analysis, IP collateral validation, design reviews, and mentoring junior engineers.

Lead consultative sales and adoption of AI Workforce solutions, including Microsoft 365 Copilot, Copilot Studio, AI agents, and related productivity technologies. Develop customer strategies, build stakeholder networks, orchestrate internal and partner teams, identify cross-sell and upsell opportunities, communicate business value, analyze competitors, and manage opportunities across territories. The role requires quota-carrying technology sales experience and success with consultative, value-based selling.

Lead architecture, development, debugging, validation, and deployment of firmware libraries for Microsoft AI accelerators and cloud silicon. Responsibilities include SoC and IP firmware design, hardware/software co-design, silicon bring-up, root-cause analysis, verification planning, performance optimization, and cross-team technical leadership. The role collaborates across hardware, software, security, validation, and systems teams, drives architecture across multiple silicon generations, establishes engineering practices, and mentors engineers.