Top Tech Jobs & Startup Jobs in Austin, TX

Design and develop platform security firmware from microarchitecture through low-level hardware interfaces. Drive architecture of security subsystems, write and debug low-level drivers, root-cause cross-subsystem firmware/hardware issues, and evaluate third-party component security to meet Azure requirements.

Lead strategic enterprise account teams to drive digital transformation, customer adoption, revenue growth, and Microsoft solution consumption. Build executive relationships, develop account and business plans, present value propositions, close complex agreements, and coordinate cross-functional teams to achieve customer and Microsoft business outcomes across AI, Copilot, Security, and the broader Microsoft portfolio.

Leads large, cross-organizational silicon, systems, and AI programs for Microsoft cloud infrastructure. Responsibilities include developing technical strategies and roadmaps, integrating AI into silicon development workflows, managing governance, risks, schedules, and releases, establishing scalable operating models and metrics, aligning executive stakeholders, and mentoring senior technical program managers. The role also partners with engineering teams to prioritize requirements, improve operational efficiency, and deliver secure, responsible AI capabilities at enterprise scale.

Leads physical implementation and layout of advanced-node D2D SerDes and analog/mixed-signal IP from floorplanning through tapeout and signoff. Owns matching-critical layout, parasitic control, integration, physical verification, reliability analysis, documentation, and production collateral. Collaborates with circuit, package, signal-integrity, ESD, CAD, foundry, and SoC teams while mentoring contributors and coordinating distributed partners. Develops analog layout automation and methodology improvements using scripting.

Leads advanced semiconductor package design for Azure hardware, including chiplet-based 2.5D/3D packaging from definition through tapeout. Manages and mentors package design engineers, drives test vehicles, reliability characterization, FMEA, EDA tool requirements, manufacturing drawings, and cross-functional architecture decisions. Oversees supplier assessments and supplier execution through qualification and production while collaborating across silicon, platform, thermal, power, performance, motherboard, and package engineering teams.

Designs and develops secure embedded firmware and hardware security architectures for Azure infrastructure. Responsibilities include HSM, security accelerator, Root of Trust, bootloader, secure boot, attestation, cryptographic, and RTOS development. The role spans architecture through validation, manufacturing, supply chain, and deployment, requiring collaboration across hardware, software, and security teams. Engineers troubleshoot complex firmware issues, optimize performance, and ensure compliance with trusted-computing security requirements.

Develops complex UVM/SystemVerilog and C++ verification environments for AI accelerator silicon at block, chip, and system levels. Creates verification plans, tests, scoreboards, assertions, constraints, and coverage models; debugs simulation and emulation failures; supports reference modeling and post-silicon validation. The role collaborates with architecture, design, firmware, validation, and product teams, while developing scalable scripts and Makefiles and applying Agile practices.

Provides end-to-end technical leadership for next-generation Azure storage hardware platforms. Drives architecture-to-execution strategy, cross-functional integration, system specifications, validation, qualification, manufacturing readiness, deployment, and fleet operations. Leads technical decisions and resolution of complex issues across hardware, firmware, software, suppliers, ODMs, datacenter engineering, and operations while managing risks, dependencies, quality, reliability, performance, security, power, cost, and schedule.

Provides technical leadership for ASIC and SoC architecture, focusing on NoC, memory, and interconnect subsystems for AI and compute platforms. Defines address maps, memory hierarchies, connectivity, and performance requirements; evaluates IP and silicon technologies; collaborates across hardware, firmware, software, design, and verification teams; and guides validation, bring-up, performance characterization, and complex system-level tradeoffs.

Leads a global Technical Program Management team responsible for firmware security, security standards, fleet protection, and automated firmware deployment and recovery. The role manages engineering efforts across the US, Taiwan, and India; partners with suppliers and internal teams; defines security features; measures business impact; and develops and retains technical talent.