Top Tech Jobs & Startup Jobs in Austin, TX

Lead end-to-end physical design from RTL to GDS for flagship silicon: synthesis, floorplanning, place-and-route, timing signoff, physical verification, EMIR, formal equivalence, and low-power verification. Coordinate across CAD, RTL/DFT, architecture, and power teams to optimize PPA, drive design flows and tooling, mentor engineers, and ensure delivery of production tape-outs.

Designs and delivers signal and power integrity solutions for HPC compute and AI SoCs, spanning silicon, packages, platforms, and systems. Responsibilities include modeling and simulating power delivery, electrical links, voltage regulators, motherboards, packages, and decoupling solutions; validating I/O performance; advancing chiplet and packaging architectures; and collaborating with silicon, platform, thermal, and power-performance teams on system design decisions.

Leads advanced semiconductor package design for Azure hardware, including chiplet-based 2.5D/3D packaging from definition through tapeout. Manages and mentors package design engineers, drives test vehicles, reliability characterization, FMEA, EDA tool requirements, manufacturing drawings, and cross-functional architecture decisions. Oversees supplier assessments and supplier execution through qualification and production while collaborating across silicon, platform, thermal, power, performance, motherboard, and package engineering teams.

Design, develop, validate, and maintain silicon debug tools and automation frameworks for pre- and post-silicon SoC bring-up. Build workflows using OpenOCD, TRACE32, JTAG/DAP, and related technologies. Develop C/C++ and Python utilities for firmware bring-up, validation, crash analysis, and system debugging. Collaborate across architecture, DFT, firmware, validation, platform, and operating system teams to diagnose hardware-software issues and enable trace collection, register and memory access, scan analysis, and remote debugging.

Leads strategic user experience research and customer co-creation workshops focused on large-scale digital and AI-powered experiences. The role designs qualitative and quantitative studies, facilitates interviews and surveys, develops foundational research strategies, manages executive stakeholders, and communicates insights through persuasive storytelling. It partners across Microsoft to define customer moments of truth, shape product direction and experience design, and deliver customer-centric solutions for enterprise clients.

Verify and validate DDR memory controller IP and subsystems by defining test plans, developing UVM/SystemVerilog and formal test environments, running/debugging simulations, applying coverage-driven/random stimulus, improving verification efficiency, using generative AI tooling, and mentoring peers to drive silicon-quality signoff.

Performs hands-on silicon debug, failure analysis, fault isolation, and yield debugging for Maia and Cobalt silicon programs. Develops debug methodologies, ensures physical and electrical tool readiness, uses ATE and analytical equipment to isolate failures, identifies root causes, and drives corrective actions across design and manufacturing test flows. The role also leads projects, manages external vendors, and coordinates cross-functional teams.

Lead development and delivery of physical design tool flows, methodologies, and sign-off for block, sub-chip, and full-chip levels of Microsoft Next‑Gen AI SoC. Responsibilities include PnR convergence, STA and timing ECOs, PV and FEV sign-off, global clocking, EM/IR analysis, IP collateral validation, design reviews, and mentoring junior engineers.

Develops complex UVM/SystemVerilog and C++ verification environments for AI accelerator silicon at block, chip, and system levels. Creates verification plans, tests, scoreboards, assertions, constraints, and coverage models; debugs simulation and emulation failures; supports reference modeling and post-silicon validation. The role collaborates with architecture, design, firmware, validation, and product teams, while developing scalable scripts and Makefiles and applying Agile practices.

Lead architecture and specification of high-performance AI accelerators. Build functional and analytical models, collaborate with hardware and software teams, and guide design, verification, emulation, firmware, and kernel teams through end-to-end silicon development to optimize performance, power, cost, and time-to-market for cloud-scale AI workloads.