Top Tech Jobs & Startup Jobs in Austin, TX

Design and optimize CPU RTL logic, simulations, and microarchitectural features for Intel processors. Develop power-, performance-, area-, and timing-efficient designs; resolve RTL test failures; document microarchitectural specifications; support physical implementation; and collaborate with architecture, verification, integration, and SoC customer teams. The role also involves clock-domain crossing, power-aware design, timing convergence, and CPU power-management considerations.

Leads full-chip floorplanning, physical integration, tapeout, and physical verification for advanced-node semiconductor testchips and silicon vehicles. Develops custom layout methodologies and automation using Tcl, Python, or SKILL; resolves DRC, LVS, DFM, density, and antenna issues; collaborates with PDK, EDA, technology development, and manufacturing teams; and coordinates tape-in readiness, database integrity, and project execution for FinFET and GAA technologies.

Conduct research in neuromorphic AI for edge computing, robotics, signal processing, control, and autonomous systems. Design algorithms, develop research software, build benchmarks, and optimize models for sparsity, latency, memory, quantization, and energy efficiency. Collaborate with hardware and software teams to define architectures, create customer prototypes, publish findings, and advance neuromorphic computing toward commercial applications.

Develop pre-silicon verification methodologies for neuromorphic SoC and ASIC architectures across software, RTL, and emulation platforms. Create Python-based directed and random tests, map application requirements to test plans, run regressions, debug failures, track coverage, maintain assertions and scoreboards, and integrate verification IPs. Collaborate with architecture, design, software, and IP teams to validate protocols and improve first-pass silicon success.

Design and optimize complex analog layouts using Cadence and Calibre tools; perform DRC/LVS and reliability checks; floorplan, power-grid, ESD and bump layout work; collaborate with circuit, process, and extraction teams to debug and improve layout quality and performance.

Lead strategy, roadmap, and execution for Intel’s data center AI software portfolio. Define enterprise-ready generative AI, agentic, microservices, and turnkey solutions across cloud, hybrid, and on-premises environments. Analyze competitors, develop go-to-market positioning, and grow relationships with cloud providers, ISVs, neoclouds, and open-source communities. Partner with engineering, AI research, silicon architecture, documentation, and developer relations teams to deliver PRDs, deployment blueprints, APIs, SDKs, and validated software offerings.

Design and develop RTL logic for CPU components and IP blocks. Contribute to CPU architecture and microarchitecture, optimize power, performance, area, and timing, support verification, resolve RTL test failures, document specifications, and assist SoC customers with CPU block integration.

Leads global accounting teams responsible for Intel’s consolidated financial close, financial statement consolidation, management reporting, cash flow reporting, and financial analysis. Oversees SEC reporting support, auditor requests, controls, process improvements, and finance transformation initiatives. Partners with senior leadership and cross-functional stakeholders to ensure accurate, timely reporting and actionable insights. The role requires CPA certification, extensive corporate accounting experience, public accounting background, and leadership of global teams.

Leads a global accounting team responsible for management reporting, balance sheet and cash flow analysis, executive reporting, and consolidated financial results. Partners on SEC filings, audits, close and consolidation processes, and cross-functional financial reporting. Drives process improvement, automation, reporting controls, and AI-enabled transformation while translating financial results into insights for senior leadership.

Verifies CPU logic and microarchitecture through test plans, test benches, simulations, and verification environments. The engineer debugs presilicon failures, analyzes power and timing, improves verification infrastructure, and collaborates with architects, RTL developers, and physical design teams to ensure functional, performance, and power objectives are met.