Top Tech Jobs & Startup Jobs in Austin, TX

The CPU Memory Design Engineer will design and develop custom memories and digital circuits for Intel CPUs, focusing on low-power and high-performance memory designs.

Design and develop custom and compiler-based memory circuits including SRAMs and caches, focusing on high-performance and low-power implementations.

Design and integrate SoC logic: develop RTL (SystemVerilog), collaborate on microarchitecture, integrate/validate IPs, optimize for power/performance/timing, support verification and pre-silicon validation, and ensure secure development and production readiness.

Design and optimize analog and mixed-signal circuits (power delivery, IPs) for advanced CMOS nodes. Perform circuit simulation, floor-planning, post-layout extraction, verification, and validation. Collaborate with architecture, layout, and validation teams, analyze test data, and iterate designs to meet power, performance, area, timing, yield, and robustness goals.

Design and implement CPU microarchitecture and RTL with emphasis on power management and energy efficiency. Develop SystemVerilog/Verilog RTL, drive PPA optimization, design CDC solutions, support DVFS, power/thermal management, reset and power-state transitions, debug complex RTL, and collaborate with verification, physical design, and SoC integration teams to deliver full-chip solutions.

The role involves architecting and leading the development of a neuromorphic AI execution stack, focusing on firmware, runtime, and performance infrastructure while collaborating with multiple teams for integration and optimization.

Design, implement, and optimize Intel's neuromorphic AI compiler and runtime. Build tooling for performance analysis, verification, debugging, and optimization. Integrate the software stack with robotics and edge AI ecosystems. Collaborate with hardware, compiler, and systems teams and external customers to deliver production-grade, high-performance software.

Seek a Senior CPU Power Management Architect for creating and ensuring optimal performance in CPU designs, focusing on power management architecture, collaboration across teams, and post-silicon debugging.

Design and optimize CPU logic and RTL, write and simulate RTL for CPU IP blocks, meet PPA and timing goals, ensure physical design integrity, review verification plans, document microarchitectural specs, and collaborate with SoC customers for integration.

Design and implement mixed-signal IP logic: RTL coding, simulation, and optimization to meet power, performance, area, and timing goals. Collaborate with analog, digital, and physical teams, review and fix RTL verification issues, and support SoC customers for high-quality IP integration.