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Lead and define end-to-end SoC functional verification strategies (simulation, emulation, formal), drive verification closure for high-speed interfaces and integrated IPs, establish reusable UVM-based methodologies, oversee emulation/prototyping, debug pre-silicon issues, mentor engineering leads, and collaborate across architecture, RTL, firmware, and post-silicon teams to ensure first-pass silicon success.

Develop, debug, and deploy density-fill components and algorithms for PDKs using industry physical verification tools (Calibre, ICV, Pegasus). Collaborate with process developers and EDA vendors, automate workflows, create test systems and documentation, and ensure manufacturability and density compliance for advanced semiconductor nodes.

Lead physical implementation of custom CPU designs from RTL to manufacturing. Execute floorplanning, synthesis, place-and-route, clock tree synthesis, STA, power/clock distribution, verification and signoff. Collaborate across architecture, logic, circuit, CAD, and validation teams to optimize power, performance, area, and manufacturability, improve physical design methodologies, and work with EDA vendors to advance tools and automation.

Design and develop RTL logic for SoC blocks, integrate IP and subsystems, optimize for power/performance/area/timing, ensure quality for physical implementation, apply secure hardware development practices, and collaborate with IP providers to validate SoC designs.

Drive yield improvement for leading-edge logic process nodes by analyzing fab, defect, and electrical data; build statistical and ML models to identify root causes; develop measurement recipes and tools; collaborate with design and factory teams to enable manufacturability and new product introductions; document procedures and support production debugging.

Design and implement DFT features (SCAN, MBIST, BSCAN) via RTL (Verilog/VHDL/SystemVerilog); provide timing closure and test content for manufacturing; collaborate across architecture, design, verification, and manufacturing; develop HVM/ATE content; verify post-silicon features; optimize power, performance, area, timing, and test coverage to meet DPM goals.

Design, develop, and optimize oneCCL communication library features for low-latency, high-throughput HPC workloads. Collaborate with scientists and hardware teams on Aurora supercomputer integrations, implement and enhance communication protocols, benchmark and analyze performance across configurations, and debug complex cross-layer hardware/software issues.

Design and optimize advanced embedded memory IP (SRAM, register files, ROM) for Intel CMOS processes. Perform memory pathfinding, PPA optimization, custom circuit design, layout and automation, pre-silicon verification and post-silicon validation/debug to enable yield and product ramp. Collaborate with domain experts, EDA vendors, and product teams to deliver memory collaterals and test chips.

The role involves analyzing user information, documenting business processes, training users, supporting testing, and managing data configurations with Windchill PLM.

The CPU Physical Design Engineer will implement custom CPU designs, conduct physical design flow, optimize designs, and collaborate on verification processes. They will work with EDA vendors and enhance methodologies for CPU design.