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Responsible for defining and validating SoC IP blocks, collaborating with teams to ensure quality silicon for AI applications, and mentoring junior engineers.

The CPU Performance Architect at Intel will design CPU logic, optimize performance and power, and collaborate with engineering teams on innovative microarchitectures for advanced computing products.

Lead development and advancement of CPU RTL front-end methodologies, leveraging AI tools to improve RTL coding, logic optimization, and cross-team collaboration. Drive strategies, tools, and techniques to meet power, performance, area, timing, and physical design targets while providing technical leadership across front-end and back-end flows.

Lead end-to-end architecture of SoC compute complexes and high-performance memory subsystems for IPU/DPU platforms. Define CPU cluster designs, cache hierarchies, coherency models, DDR/HBM memory controllers, SMMU/IOMMU virtualization, and system-level integration with networking, storage, and accelerators. Optimize performance, power, scalability, and multi-generation roadmaps while collaborating across firmware, drivers, validation, and performance teams.

Lead end-to-end network subsystem architecture for next-generation IPU/DPU SoCs, defining packet pipelines, protocol engines, QoS/scheduling, telemetry, and scalability. Drive cross-functional architecture decisions, customer engagements, and multi-generation roadmap for hyperscale data center networking.

Lead architecture strategy for multi-die chiplet SoC platforms: define chiplet partitioning, D2D interconnect and QoS, power/clock/boot infrastructure, RAS/debug/telemetry, and system-level PPA/cost/yield trade studies. Drive cross-functional alignment and produce executive architecture recommendations for scalable data-center networking SoCs.

Define and own adapter/IPU/DPU/NIC card and platform architectures, driving integration across SoC, board, firmware, OEMs and data center requirements. Specify manageability, thermal/power, reliability, and serviceability; lead cross-functional reviews and deliver actionable architecture artifacts and roadmaps.

Drive performance verification and circuit quality signoff for CPU designs, evaluate new process nodes, and manage pre-to-post silicon correlation and debugging. Requires experience in circuit design and STA.

As a Senior Formal Verification Engineer, you will develop verification strategies and environments for AI SoCs, ensuring the correctness of digital designs through formal verification methods and collaboration with engineering teams.

The role involves physical design implementation of custom CPU designs, including synthesis, static timing analysis, verification, and collaborating to optimize CPU parameters. Leadership and communication skills are essential.