Top Tech Jobs & Startup Jobs in Austin, TX

Develop and maintain Intel’s asynchronous EDA design automation flow for neuromorphic silicon. Build algorithms, tools, utilities, scripts, and regression tests supporting RTL, verification, physical design, simulation, FPGA emulation, synthesis, and implementation. Create scalable frameworks for early software development and optimize custom low-power, high-performance designs. The role requires full ASIC lifecycle knowledge, multiple tape-outs, strong scripting skills, and experience using AI-assisted engineering tools.

Lead DFT/DFX strategy for Intel’s neuromorphic silicon program, architecting SoC-level test solutions across synchronous and asynchronous designs. Develop scan insertion, compression, ATPG, test-vector, emulation, and validation flows; collaborate on DFT, DFD, and DFM features for high-volume manufacturing. Lead silicon power-on, tester-content enablement, failure debugging, and reliability improvements while maintaining development tools and flows.

Drives CPU performance verification methodology, circuit and timing quality signoff, process-node evaluation, frequency target recommendations, and performance, power, and area tradeoffs. Collaborates with RTL, circuit, and design teams to meet timing targets. Owns pre-to-post-silicon verification correlation and debugs circuit marginality. Requires advanced CPU circuit or backend design experience, circuit design and STA expertise, and strong execution and technical ownership.

As a Senior Formal Verification Engineer, you will develop verification strategies and environments for AI SoCs, ensuring the correctness of digital designs through formal verification methods and collaboration with engineering teams.

Design and execute verification plans and UVM-based testbenches to validate CPU logic and microarchitecture. Run system-level simulations, debug pre-silicon issues, collaborate with architects and RTL designers, maintain verification infrastructure, and document strategies to ensure functional, performance, and power goals are met.

Develop CPU architecture specifications, innovate designs for various computing segments, collaborate across teams, and debug microarchitectural issues.

The CPU Performance Architect will define CPU architectures, model performance, analyze bottlenecks, collaborate on designs, and resolve microarchitecture issues to enhance CPU efficiency.

Design, develop, and optimize oneCCL communication library features for low-latency, high-throughput HPC workloads. Collaborate with scientists and hardware teams on Aurora supercomputer integrations, implement and enhance communication protocols, benchmark and analyze performance across configurations, and debug complex cross-layer hardware/software issues.

Design and implement CPU RTL for integer, floating point, and reservation station logic. Drive RTL coding, simulation, and optimization for power, performance, area, and timing. Participate in architecture definition, review verification plans, resolve RTL test failures, and provide technical leadership and cross-team collaboration to deliver CPU IP for full-chip integration.

Lead front-end RTL methodology for CPU design, leveraging AI tools to improve RTL coding, debug, and logic optimization. Drive methodology and architectural discussions, collaborate with architecture and backend teams, and deliver CPU IP meeting power, performance, area, and timing goals. Provide technical leadership and build a high-performing team.