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Characterize semiconductor device behavior and develop/update compact device models for new technologies. Validate and ensure accurate, robust model simulations, support design enablement, and collaborate with process and design teams using scripting and simulation tools.

Develop and maintain full-chip physical implementation flows for SoC designs, including floorplanning, partitioning, hierarchical block integration, placement and routing coordination, power grid planning and IR analysis, CTS strategy integration, and scalable multi-block/multi-power-domain assembly methodologies using Innovus.