Top Tech Jobs & Startup Jobs in Austin, TX

Design and implement CPU RTL for integer, floating point, and reservation station logic. Drive RTL coding, simulation, and optimization for power, performance, area, and timing. Participate in architecture definition, review verification plans, resolve RTL test failures, and provide technical leadership and cross-team collaboration to deliver CPU IP for full-chip integration.

Lead front-end RTL methodology for CPU design, leveraging AI tools to improve RTL coding, debug, and logic optimization. Drive methodology and architectural discussions, collaborate with architecture and backend teams, and deliver CPU IP meeting power, performance, area, and timing goals. Provide technical leadership and build a high-performing team.

Define end-to-end CPU architecture and microarchitecture features, set performance/power/area targets, model and analyze CPU performance and power, develop tests and simulations, specify new instructions, and collaborate with design, verification, and validation teams to deliver optimized CPU designs across product segments.

The role involves architecting and leading the development of a neuromorphic AI execution stack, focusing on firmware, runtime, and performance infrastructure while collaborating with multiple teams for integration and optimization.

Lead physical design timing efforts for next-generation SoCs: perform timing analysis and optimization, generate and validate timing constraints, define PVT conditions, develop timing models and flows, collaborate with clocking, architecture, and logic teams to ensure high-performance, low-power chip integration.

The CPU Performance Architect at Intel will design CPU logic, optimize performance and power, and collaborate with engineering teams on innovative microarchitectures for advanced computing products.

Develop and maintain transistor-level electromigration (EM) and IR drop analysis flows for custom IP, SRAM, analog/mixed-signal interfaces, and high-performance macros. Build CAD methodology, automation infrastructure, and power-integrity signoff flows, perform silicon correlation, and collaborate with circuit design, physical design, package, reliability, and signoff teams to enable scalable, accurate reliability verification using industry EM/IR tools.

Develop and maintain full-chip physical implementation flows for SoC designs, including floorplanning, partitioning, hierarchical block integration, placement and routing coordination, power grid planning and IR analysis, CTS strategy integration, and scalable multi-block/multi-power-domain assembly methodologies using Innovus.