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Develop and optimize DFT architectures for ASICs, performing validation, integration, and test pattern generation, while collaborating with cross-functional teams.

Develop next-generation ASICs for SpaceX's Starlink system, evaluate architectural trade-offs, and ensure design verification and integration with physical implementation teams.

Develop next-gen ASICs for space deployment, perform design implementation, collaborate with teams, and resolve timing/congestion issues in chip development.

The engineer will handle full-chip physical verification, including DRC, LVS, and ESD signoff, while optimizing design flows for advanced SoCs and engaging with foundry teams.

Develop next-generation silicon for SpaceX's Starlink initiative, performing physical implementation steps, improving methodologies, and collaborating with design teams.

The Sourcing Manager will create sourcing strategies, manage suppliers, develop stakeholder relationships, analyze financial impacts, and lead contract negotiations and purchasing efforts while ensuring compliance and performance metrics.

The Principal DFT Engineer will lead DFT architecture optimization, test pattern generation, and integration of DFT into ASICs for SpaceX's Starlink project, collaborating with cross-disciplinary teams.

Develop and verify digital ASIC designs for SpaceX's Starlink project, focusing on verification methodologies and test bench development.

The Sr. IC Package Design Engineer will lead advanced package selection for ASICs, manage design verification, and collaborate with cross-functional teams for optimal silicon integration.

The Principal Design Verification Engineer will verify ASICs/FPGA designs, lead test plans, and ensure designs meet specifications. Collaborating with cross-disciplinary teams, the role involves pre-silicon verification and post-silicon validation.