Top Tech Jobs & Startup Jobs in Austin, TX

Own NVIDIA’s config-as-code foundation for its EDA compute farm. Design LSF deployment schemas, build federated deployment pipelines with staged rollout and rollback, eliminate configuration drift, and create regression testing for scheduled LSF upgrades. Partner with an LSF specialist to encode scheduler expertise into templates and policies. The role also requires infrastructure automation, GitOps at scale, tooling development in Go, Python, and shell, and management of stateful production infrastructure.

Develop compiler verification software and infrastructure for deep learning compilers. Analyze graph transformations, IR lowering, fusion, mixed-precision optimizations, and GPU execution for semantic and numerical correctness. Build test-generation systems across model topologies, precision modes, and hardware targets, while improving functional quality and performance measurement. Collaborate with compiler and architecture teams to investigate correctness issues and edge-case failures.

Lead security engineering for RTOS, hypervisor, and embedded virtualization: design and review defenses, collaborate on CPU/SoC security, perform threat modeling and automotive TARA, review low-level C/C++ code, build fuzzing and test infrastructure, assess vulnerabilities, and drive security fixes and verification toward automotive safety and security standards.

Lead development and improvement of ASIC integration, build, simulation, CI, and debug infrastructure for high-speed IO GPU IP. Apply automation, metrics, and AI-assisted workflows to improve reliability, turnaround, and debuggability. Collaborate across design, verification, firmware, methodology, and infrastructure teams to root-cause failures and deliver durable process improvements.

Develop simulation infrastructure for evaluating deep learning workloads across NVIDIA GPUs and compiler stacks. Optimize compiler kernel code generation, computational graphs, and datacenter-scale AI deployments using performance modeling. Collaborate with architecture, software, product, and research teams to assess future GPU features and influence silicon and system design. The role requires strong MLIR, C/C++, and Python expertise, along with experience in compiler optimization, architectural simulation, or related areas.

Lead pre-silicon system software bring-up and validation on simulation platforms. Develop automation, tools, and workflows to improve simulation-based development, debug complex cross-stack issues, enable teams to use virtual platforms, and drive platform readiness for new chips in early-development environments.

Develop and maintain automated SDK tests, OS verification infrastructure, CI/CD workflows, and release automation. Collaborate with hardware, firmware, DevOps, and software teams to debug issues, improve test coverage and stability, and build expertise in networking technologies. The role requires strong Python, Linux, Git, and CI tool experience, with networking, test frameworks, Docker, and infrastructure-as-code knowledge preferred.

Develop CUDA compiler front-end capabilities, including language features, diagnostics, semantic analysis, and code generation. Improve compiler feedback for developers and AI agents, track evolving C++ standards, and contribute across LLVM optimization, code generation, and MLIR. Collaborate with compiler, library, and developer tools teams to deliver robust production software.

Develop scalable system-level methodologies and automation tools for SOC creation. Identify and resolve inefficiencies in front-end chip implementation, own RTL quality checks and reviews, and collaborate with ASIC, physical design, CAD, package design, software, and DFT teams. The role requires expertise in SOC integration, RTL design and verification, design automation, scripting, synthesis, and physical design workflows.

Develops timing signoff strategies for advanced GPUs, CPUs, LPUs, and SoCs. Runs large-scale SPICE and STA experiments, builds STA and PNR flows, models advanced-node effects, and improves timing, power, yield, and reliability. Collaborates with technology, physical-design, and timing teams while developing automation and data-analysis methods using Python, JMP, Tcl, and industry-standard EDA tools. The role supports advanced FinFET and emerging CMOS technologies, including 3D IC integration and die stacking.