Top Tech Jobs & Startup Jobs in Austin, TX

Lead development and optimization of verification infrastructure and test suites for Ethernet switch SDKs. Collaborate with hardware, firmware, DevOps, and software teams to build CI/CD pipelines, dashboards, benchmarks, and automation for pre/post-silicon validation. Guide architecture, coordinate global verification projects, and mentor junior engineers.

Partner with architecture and design teams to plan and execute functional and performance verification for GPU memory subsystem IP. Develop testbenches, BFMs, monitors and regressions, close coverage, enable FPGA/software testing, and support post-silicon verification and debug to sign off RTL.

The role involves developing and implementing features for the CUDA driver and collaborating on solutions for NVIDIA's compute platform, requiring strong coding and design skills.

Provide first-line support and troubleshooting for an HPC environment, monitor system health, triage incidents, perform maintenance and patching, and produce runbooks and documentation. Improve processes and escalate to SMEs for complex issues while supporting scheduling, compute, storage, and access concerns.

Lead and grow the Isaac Manipulation engineering team to deliver production-grade robotic manipulation capabilities. Define roadmap, bridge research and product, partner with OEMs and developers, leverage NVIDIA GPUs/CUDA/PyTorch and simulation for sim-to-real learned policies, and drive delivery of manipulation stacks onto physical robots.

The role involves integrating CUDA features into AI frameworks, optimizing performance, and collaborating with teams on AI model development. Responsibilities include design, analysis, and enhancement of AI tools and frameworks.

Lead development of memory system architecture and micro-architecture for SoCs. Build and maintain performance models and simulations, analyze benchmarks and workloads, identify micro-architectural tradeoffs, and debug performance and functional issues across high-level models, RTL simulation, and silicon.

Design and architect on-chip GPU/CPU clock domains, collaborate with front-end, physical design, timing, verification and SW teams to implement clock RTL, optimize PPA, support ASIC implementation through sign-off and silicon bring-up.

Develop and invent parallel, graph-based RTL analysis and optimization methods. Analyze RTL impacts on latency, power, DFT, clocking, and power delivery. Explore ML (LLMs, GNNs, GANs, RL) and high-performance algorithms for logic synthesis, clustering, and implementation. Drive end-to-end tool development and collaborate with design teams to deploy optimizations.

Design and implement LLM-first APIs and documentation for CUDA-X math libraries. Develop tools, metrics, and processes to improve AI-agent code generation and transform library APIs into LLM-friendly formats. Collaborate with stakeholders on LLM-enhanced releases while prototyping solutions for code-generation platforms. Requires expertise in LLMs, fine-tuning, reinforcement learning, RAG, MCP, agent tooling, composable API design, and technical documentation.