Top Tech Jobs & Startup Jobs in Austin, TX

Design and build a scalable failure-attribution framework for heterogeneous CPU/GPU clusters: collect high-fidelity telemetry, implement low-overhead tracing, automate root-cause classification (hardware, software, environment), and enable proactive resiliency measures like migration or checkpointing.

As a Senior Software Engineer at NVIDIA, you will enhance HPC infrastructure, improve systems reliability, and optimize cloud operations, focusing on distributed systems and automation.

Lead customer-facing quality assurance for hardware products: manage customer communications, audits, metrics, and crisis response; drive root-cause analysis, corrective/preventive actions, cross-functional coordination, and continuous improvement to increase customer satisfaction.

The Senior Memory Controller Verification Engineer will develop verification infrastructure, drive test plans, ensure coverage, and assist with post-silicon verification for NVIDIA's GPU Memory Subsystem.

As a Senior Product Engineer, you will analyze failures, design experiments, collaborate with teams, and innovate solutions to enhance product quality and performance in NVIDIA's networking products.

Lead research and architectural direction for AI systems communication at scale, conducting original research, optimizing hardware-software performance, and mentoring engineers.

Lead the design and implementation of GPU compute clusters for deep learning and high-performance workloads, manage large-scale systems and ensure efficient resource utilization.

Lead custom SRAM and memory IP physical layout from floorplanning through DRC/LVS-clean tapeout in advanced CMOS nodes. Produce and review complex layouts, debug physical verification issues, support EM/IR and DFM closure, collaborate with circuit, PnR, CAD, foundry teams, and mentor junior engineers to advance layout methodology and quality.

Develop and deliver system-level IP and RTL to measure performance on GPUs/SOCs. Create and automate flows, run/debug RTL checks (CDC, clocks, resets, latency), implement RTL features, and collaborate with architects, designers, and software engineers to support projects and performance monitoring.

As an EDA Workflow Optimization Engineer, you will optimize and enhance workflows for chip development, working with teams to investigate, debug, and innovate tools for efficient engineering processes.