Top Tech Jobs & Startup Jobs in Austin, TX

The Senior Hardware SoC Architect defines clock and reset architecture for SoC, collaborates with various teams, and improves methodologies and C-models.

Design and develop software solutions for data center servers, focusing on Linux kernel modifications, device drivers, and system optimizations while directly collaborating with Cloud Service Providers.

The Senior CPU Performance Architect will drive the development of CPU technology focusing on performance analysis for AI, HPC, and GPU-accelerated workloads, while collaborating with architects to enhance CPU designs.

The Senior ASIC Design Engineer will design high-performance RTL for next-gen Switch Silicon chips, analyze architectural trade-offs, and collaborate with various engineering teams.

Design and build a scalable failure-attribution framework for heterogeneous CPU/GPU clusters: collect high-fidelity telemetry, implement low-overhead tracing, automate root-cause classification (hardware, software, environment), and enable proactive resiliency measures like migration or checkpointing.

Lead design and implementation of a scalable observability and data platform: build high-performance ingestion, governance and policy systems, unified web APIs/UX, tiered storage, and automation for lifecycle and pipeline orchestration to support NVIDIA engineers at scale.

The Senior Formal Verification Engineer will verify GPU micro-architecture, implementing test plans with formal techniques, debugging RTL, and improving team efficiency.

Design, build, and operate global, multi-cloud HPC service platforms. Own IaC-driven provisioning, reliability, observability, capacity planning, incident response, and automation to ensure high uptime and QoS for internal customers.

Contribute to power estimation models for GPUs, analyze performance vs power, and deploy machine learning techniques in GPU architectures.

As a Senior ASIC Design Engineer, you will architect GPU/CPU clock domains, collaborate across teams for design requirements, and improve clocking topologies while ensuring design fixes and silicon debug support.