Top Tech Jobs & Startup Jobs in Austin, TX

Develop physical design methodologies for rail analysis and signoff, craft workflows for power and noise analysis, and provide creative solutions for IR analysis needed for NVIDIA chips.

Design and develop RTOS and hypervisor features, bring up and optimize software stacks on NVIDIA Tegra SoCs, and debug system-level issues across hardware, firmware, RTOS, and virtualization layers. The role develops high-integrity automotive software using safety and security practices, while leading cross-team technical initiatives and coordinating execution. Candidates need strong C/C++ systems programming, embedded software expertise, operating-system knowledge, hardware-assisted virtualization experience, and at least eight years of experience.

Owns multi-generation system power and performance architecture for datacenter and high-performance platforms. Defines HSIO power management, DVFS, P-state, low-power, boot, initialization, reset, and recovery strategies across silicon, firmware, ASIC, board, and platform teams. Drives rack-scale power telemetry and platform coordination, diagnoses system-level performance and power issues, and influences roadmap and product decisions through silicon correlation and release. The role requires deep technical ownership, cross-functional authority, and experience delivering architectures across multiple silicon generations.

Develop and enhance network hardware and software profiling tools using C/C++ and Python. Collaborate with customers, architects, hardware and software engineers, and operations teams to define requirements, design solutions, and deliver tools for optimizing complex GPU, CPU, and networking systems across HPC, cloud, AI, embedded, and automotive environments.

Develop simulation infrastructure for evaluating deep learning workloads across NVIDIA GPUs and compiler stacks. Optimize compiler kernel code generation, computational graphs, and datacenter-scale AI deployments using performance modeling. Collaborate with architecture, software, product, and research teams to assess future GPU features and influence silicon and system design. The role requires strong MLIR, C/C++, and Python expertise, along with experience in compiler optimization, architectural simulation, or related areas.

Design and implement production-grade VLSI/EDA tools and methodologies for multi-die package design. Build flows, applications, and automation to construct, analyze, validate, and optimize package designs to accelerate tape-out and scale engineering teams.

Design and implement reliable, scalable full‑stack web tools (backend and frontend) to automate and optimize chip design and verification workflows. Build web applications in Go, TypeScript, and JavaScript, model hardware-level product definitions, research solutions to improve engineering efficiency, and support hundreds of global users.

Lead performance characterization and optimization of large-scale AI workloads across GPUs, networking, storage, and software. Design and run benchmarks and profiling, diagnose bottlenecks, define evaluation methodologies and metrics, produce actionable optimization plans, and collaborate with DL engineers, platform teams, and GPU architects to deliver improvements.

Lead the optimization and performance analysis of distributed training and inference workloads on NVIDIA GPU platforms, with responsibilities including debugging, benchmarking, and ensuring reliability of large-scale AI systems.

Develop physical design methodologies for graphics processors and SOCs, focusing on innovative solutions to PPA problems and ML-based development.