Top Tech Jobs & Startup Jobs in Austin, TX

Lead technical performance analysis and optimization of large-scale AI/HPC clusters. Diagnose cross-component bottlenecks, build and maintain benchmarking suites, collect and transform telemetry into time-series dashboards, and collaborate with engineering, field teams, and customers to resolve configuration and performance issues.

Develop and improve C++ algorithms and optimization engines for VLSI physical design (sizing, buffering, CTS, legalization, ECO routing). Own discovery through deployment, collaborate with design teams, and optimize for frequency, power, and performance using EDA tools and scripting flows.

Develop and support software tools for chip design and verification, optimize workflows, work collaboratively to create high-performance software.

Drive physical design and timing for high-frequency, low-power CPUs/GPUs/SoCs from RTL to GDS2. Perform synthesis, STA, timing constraint generation, timing convergence, placement/routing optimizations, ECO implementation, DFT closure, and cross-team methodology improvements to achieve timing and power targets.

Develop silicon-accurate GPU kernel microbenchmarks, model-level performance analysis, and agentic kernel optimization to maximize LLM inference throughput and latency. Attribute bottlenecks across kernel, compiler, and runtime, produce optimization policies, and collaborate with compiler, hardware, kernel, and framework teams to deliver production-grade performance improvements.

Own and optimize IBM Spectrum LSF scheduling across 15–25 federated cells. Diagnose scheduler latency, MultiCluster forwarding and cross-cluster contention, design scalable cell topology, and encode scheduler policy through infrastructure as code. Partner with CAD and methodology teams on large-scale EDA workloads, license constraints, and tape-out bursts. Requires deep LSF internals expertise, production MultiCluster experience, strong Linux fundamentals, and Python, Perl, and shell scripting skills.

Own NVIDIA’s config-as-code foundation for its EDA compute farm. Design LSF deployment schemas, build federated deployment pipelines with staged rollout and rollback, eliminate configuration drift, and create regression testing for scheduled LSF upgrades. Partner with an LSF specialist to encode scheduler expertise into templates and policies. The role also requires infrastructure automation, GitOps at scale, tooling development in Go, Python, and shell, and management of stateful production infrastructure.

Develops timing signoff strategies for advanced GPUs, CPUs, LPUs, and SoCs. Runs large-scale SPICE and STA experiments, builds STA and PNR flows, models advanced-node effects, and improves timing, power, yield, and reliability. Collaborates with technology, physical-design, and timing teams while developing automation and data-analysis methods using Python, JMP, Tcl, and industry-standard EDA tools. The role supports advanced FinFET and emerging CMOS technologies, including 3D IC integration and die stacking.

Design and implement CUDA Tile compiler transformations, MLIR dialects, lowering passes, and optimization techniques for NVIDIA GPUs. Optimize tile-based kernel performance across GPU generations, define public APIs, conduct performance analysis, and develop robust software, tests, and debugging workflows. The role requires independent project ownership and collaboration within a product-focused engineering team.

The role involves validating clocking structures in products, developing test plans, automation, and partnering with design teams to ensure high-quality verification of ASIC designs.