Top Tech Jobs & Startup Jobs in Austin, TX

Lead development and optimization of NVIDIA’s Aerial platform for software-defined 5G/6G RAN systems. Develop baseband software in C, C++, Python, and CUDA; optimize CPU, GPU, and NIC performance; troubleshoot and integrate complex modules; conduct testing, demonstrations, benchmarking, and lab trials; and collaborate with engineering teams, customers, and telecommunications partners on system integration and technical solutions.

Analyze and optimize distributed machine-learning training and inference performance across models, frameworks, compilers, kernels, GPUs, networks, and hosts. Define fleet-wide performance metrics, diagnose regressions, evaluate automated diagnoses, build reusable analysis methods, and collaborate with partners to improve workloads and product capabilities. The role requires strong programming, debugging, statistical judgment, and communication skills, with proficiency in Python and CUDA.

Develop and maintain performance instrumentation requirements, tracing, telemetry, validation, and alerting systems for production machine learning and systems software. Identify visibility gaps, design low-overhead instrumentation APIs, measure observer effects, ensure data quality, and collaborate across teams to deliver code changes. The role requires debugging across component boundaries, validating changes through testing and measurement, and balancing overhead, fidelity, sampling, and aggregation.

Develop and tune GPU workloads, AI training and inference workloads, performance models, automated validation, and system-level experiments for NVIDIA DGX platforms. Analyze telemetry, performance anomalies, workload correctness, and hardware/software failures; build automation for deployment, testing, and analysis. Collaborate with architecture, hardware, and software teams to improve performance, validation coverage, and product quality.

Build and operate large-scale data systems for analyzing AI workload performance across GPU data centers. Responsibilities include designing data stores, models, query paths, streaming pipelines, APIs, data contracts, access controls, and evidence views. The role requires managing telemetry and profiling data, ensuring correctness with delayed or duplicated inputs, optimizing latency and storage efficiency, and validating performance improvements through measurement.

Design and optimize custom SRAM circuits for NVIDIA processing chips, balancing performance, area, and power. Collaborate with mask designers on dense layout, verify functionality and electrical robustness, and improve design automation and analysis flows. The role requires strong SRAM and memory design expertise, scripting skills, and experience with circuit design methodologies and industry tools such as Cadence Virtuoso and SPICE simulators.

Develop physical design methodologies and automation for NVIDIA graphics processors, CPUs, GPUs, and SoCs. Run PPA experiments involving floorplanning, clock and power distribution, place and route, timing closure, power and noise analysis, and back-end verification. Address hierarchical design, physical convergence, yield and manufacturability, EM/IR closure, thermal management, and technology scaling using industry-standard EDA tools and scripting languages.

Design, build, and operate Go and Python tooling that validates GPU clusters across Kubernetes and Slurm. Develop certification systems, benchmarks, workload catalogs, provenance and evidence pipelines, platform integrations, and signed auditable results. Investigate performance and correctness issues across distributed AI infrastructure, contribute to open-source projects, and author technical documentation. The role requires deep Linux, container, Kubernetes, HPC, GPU, and distributed-systems expertise, with collaboration across internal teams and cloud partners.

Own the silicon architecture and construction plans for next-generation CPU processors. Responsibilities include exploring 2D, 2.5D, and 3D dielet configurations; planning floorplans, die-to-die interfaces, and off-chip I/O such as UCIe, DRAM, and PCIe; and collaborating with architecture, logic design, physical design, and packaging teams to meet area, performance, power, and thermal objectives.

Design and implement high-performance, low-power CPU subsystems. Define microarchitecture, develop RTL, optimize logic for performance, timing, and power, and deliver synthesis- and timing-clean designs. Collaborate with verification and physical design teams on floor planning, power and clock distribution, timing closure, noise analysis, chip assembly, and back-end verification. Develop supporting design flows and tools as needed.