Top Tech Jobs & Startup Jobs in Austin, TX

Develop scalable system-level methodologies and automation tools for SOC creation. Identify and resolve inefficiencies in front-end chip implementation, own RTL quality checks and reviews, and collaborate with ASIC, physical design, CAD, package design, software, and DFT teams. The role requires expertise in SOC integration, RTL design and verification, design automation, scripting, synthesis, and physical design workflows.

Develop and improve NVIDIA's proprietary GPU compiler backend in C++. Design and implement compiler passes and optimizations, collaborate with hardware and application teams, and support graphics and compute toolchains for high-performance GPU instruction generation.

Develop and improve NVIDIA’s proprietary GPU compiler backend in C++. Design register allocation passes and compiler optimizations for high-performance GPU machine instructions. Collaborate with compiler, hardware, and application teams on improvements and issue resolution. The role spans deep-learning compiler technology and requires strong compiler code-generation experience, preferably with LLVM, plus robust software engineering, testing, and documentation skills.

Verify ASIC designs and high-speed I/O controllers at IP, subsystem, and SoC levels using UVM and coverage-driven methodologies. Develop reusable models, monitors, checkers, scoreboards, test plans, tests, and verification infrastructure. Perform random-stimulus, functional-coverage, assertion-based verification and debugging while collaborating with architects, designers, and pre- and post-silicon teams. Relevant protocols include Ethernet, NVLink, USB, SATA, and CXL.

Lead development and validation of LLM inference platforms for NVIDIA edge GPUs. Track open-source framework innovations, analyze model-to-hardware mapping, optimize GPU kernels and multi-node inference, produce performance reports, maintain developer inference recipes, own model bring-up workflows, and support partners on hardware-specific inference issues.

Drive physical design for CPUs, GPUs, and SoCs focusing on netlist-related tasks, logic synthesis, and timing closure. Help in ECO generation.

Design, develop, test, and optimize system software for next-generation ARM SoCs in pre- and post-silicon phases. Analyze system-wide performance bottlenecks, recommend HW/SW policies, perform competitive workload comparisons, and drive full-stack adoption of performance optimizations across NVIDIA software and OSS SDKs.

Serve as technical lead between NVIDIA and hyperscale CSPs on GPU firmware and system software. Drive firmware update orchestration, recovery procedures, multi-GPU coordination, telemetry/health monitoring, and incorporate CSP feedback into NVIDIAs roadmap to improve fleet-scale manageability and reliability.

Serve as NVIDIA's CSP-facing principal for end-to-end performance: drive characterization with hyperscaler engineering teams, gather and synthesize workload feedback, prioritize optimizations across CUDA/NCCL/driver/firmware, validate benchmarks and tools, update stress/profiling tooling, define test strategies, and ensure performance integration and acceptance for customer-representative configurations.

Drive physical design of high-frequency, low-power CPUs/GPUs/SoCs at block, cluster, or full-chip level with emphasis on netlist quality: equivalence checking/formal verification, CDC and MTBF analysis, logic synthesis, timing convergence, STA, constraint generation/management, and ECO implementation. Use industry-standard EDA tools and scripting to debug and improve flows.