Top Tech Jobs & Startup Jobs in Austin, TX

The role involves developing and integrating energy modeling tools for NVIDIA's chips, analyzing algorithms, and improving power efficiency through data analysis and machine learning.

The role focuses on optimizing and managing workload scheduling systems for EDA, enhancing observability, service reliability, and automation while resolving performance issues.

The role focuses on optimizing communication performance for deep learning systems, designing protocols, and collaborating on hardware/software integration while exploring innovative technologies.

The Senior Software Architect will design and implement communication technologies, improve performance for AI and HPC workloads, and lead innovative GPU communication solutions.

The EDA Methodology Architect will define the RTL2GDS flow, collaborate on optimizing designs, analyze performance issues, and drive new methodologies across teams.

The role involves defining architecture for NVLink Fusion, collaborating with customers, mentoring teams, and managing software abstraction layers.

Develop and debug cloud-native solutions for AI/ML datacenters, focusing on Kubernetes and Slurm enhancements and customer workflows.

Design and implement algorithms and tools for chip-level placement, reshaping, and global routing. Develop computational geometry, placement, routing and graph-optimization solutions, apply machine learning for design space exploration, extend GUIs for debugging/visualization, and collaborate with design teams to deploy high-performance C++ tools impacting next-generation AI chip physical layouts.

Verify SoC and GPU design, architecture and micro-architecture using advanced methodologies. Define verification scope and infrastructure for memory subsystems, verify firmware and hardware/firmware interactions, develop reusable verification components and plans, debug issues, and collaborate with architects, designers, and software engineers across sites.

Responsible for physical design and implementation of GPUs and ASICs, including methodology establishment, power/clock distribution, and timing closure.