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The Senior Software Architect will design and implement communication technologies, improve performance for AI and HPC workloads, and lead innovative GPU communication solutions.

The ASIC Verification Engineer will develop and automate verification test plans, ensuring code coverage and collaborating with teams on design verification processes. This role requires strong analytical and debugging skills with experience in RTL verification methodologies.

Lead development of AI-driven solutions for timing and constraint analysis in EDA, integrating data sources and creating autonomous analysis agents.

You will integrate communication libraries into AI frameworks, analyze workloads, improve AI compilers, and author custom kernels for performance.

Develop optimization engines for VLSI physical design at NVIDIA, focusing on algorithms in C++ for timing optimization, with significant hardware and software collaboration.

Design and implement an LLVM-based backend JIT compiler for NVIDIA GPUs. Develop compiler passes and optimizations, focusing on high performance and low compile time. Collaborate with hardware, compiler, and application teams to resolve issues and influence future GPU architectures.

Lead development and improvement of ASIC integration, build, simulation, CI, and debug infrastructure for high-speed IO GPU IP. Apply automation, metrics, and AI-assisted workflows to improve reliability, turnaround, and debuggability. Collaborate across design, verification, firmware, methodology, and infrastructure teams to root-cause failures and deliver durable process improvements.

Develop and prototype high-performance CUDA-based deep learning systems and custom kernels. Architect and optimize distributed, cluster-scale training and inference pipelines, analyze hardware-software performance bottlenecks, build profiling and runtime tools, and collaborate with researchers, compiler and driver teams to transition prototypes into frameworks or products.

Responsible for analyzing architectural requirements, delivering high-performance RTL blocks, collaborating with engineers, and assisting in IP solution integration.

The role involves driving timing analysis and closure for NVIDIA's hardware, collaborating with cross-functional teams, and contributing to advanced technology projects.