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The ASIC Verification Engineer will develop and automate verification test plans, ensuring code coverage and collaborating with teams on design verification processes. This role requires strong analytical and debugging skills with experience in RTL verification methodologies.

Lead development of AI-driven solutions for timing and constraint analysis in EDA, integrating data sources and creating autonomous analysis agents.

You will integrate communication libraries into AI frameworks, analyze workloads, improve AI compilers, and author custom kernels for performance.

The role involves designing, building, and deploying compute and networking solutions for AI and HPC, supporting customers with integration and performance debugging.

Develop innovative physical design methodologies for GPUs and SOCs, focusing on PPA improvements and collaboration across multiple teams. Use AI/ML to enhance design efficiency.

Lead engineering team to develop AIPerf, an open-source benchmarking tool for LLM inference performance, while overseeing technical direction and mentoring engineers.

Develop optimization engines for VLSI physical design at NVIDIA, focusing on algorithms in C++ for timing optimization, with significant hardware and software collaboration.

The role involves validating clocking structures in products, developing test plans, automation, and partnering with design teams to ensure high-quality verification of ASIC designs.

The role involves designing and maintaining verification environments, developing test plans, creating UVM components, launching regressions, and collaborating with engineers to ensure high-quality IP delivery.

The role involves developing test plans, implementing verification infrastructures, and collaborating with design teams to ensure the correctness of global IP across multiple products.