Top Tech Jobs & Startup Jobs in Austin, TX

As a Senior AI Compiler Engineer, you'll design and implement MLIR-based compilers for 5G/6G silicon, ensuring high precision in hardware-specific IR generation and memory management with a focus on advanced compiler techniques.

Work as an intern on 5G baseband software and embedded systems, integrating AI/ML models, developing signal-processing algorithms, testing LTE/5G systems, and collaborating across teams using agile practices.

The Principal AI Compiler Engineer designs hardware for AI, ensuring models translate effectively to silicon and perform optimally in 5G applications.

The Principal AI Model Architect's role includes optimizing model architectures for new hardware, translating AI algorithms into hardware specifications, and projecting performance for silicon design.

The ASIC RTL Design Engineer will design and verify RTL for complex ASICs, collaborating on cross-functional initiatives and optimizing circuits from specification to silicon.

Define and implement the physical design flow; drive IP and SoC physical design execution; collaborate with CAD and cross-disciplinary teams; mentor and hire engineers; work hands-on with advanced process nodes to achieve PPA, power, and timing signoff.

Lead physical design for high-performance ASICs/SoCs, improving PPA, evaluating architecture feasibility, addressing timing/power/congestion, delivering synthesized netlists to BE vendors, guiding junior engineers, and defining/optimizing design flows and constraints.

The Data Center Engineer is responsible for optical testing, hardware replacement, cabling, troubleshooting, and ensuring optimal data center operations.

As a Senior AI Compiler Engineer, you will design and build a custom MLIR-based compiler stack for next-gen silicon, optimizing AI models without an OS. Responsibilities include creating MLIR dialects, ensuring accuracy in lowering computational graphs, and maintaining a high-performance compiler codebase.

The IP Verification Engineer will lead verification efforts for ASIC IP, build environments, mentor team members, and ensure designs meet specifications in 5G infrastructure.