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Leads and develops a Technical Program Management organization responsible for post-silicon execution across complex Arm-based SoC programs. Oversees silicon validation, bring-up, debug, production readiness, integrated planning, risk management, dependencies, governance, and milestone execution. Partners with hardware, firmware, software, architecture, and external development teams while influencing senior leadership, improving operational rigor, and resolving cross-functional challenges.

Architect high-speed PCIe, CXL, and UA Link interconnect subsystems for scalable Arm-based SoCs. Define technology roadmaps, develop implementation-ready specifications, integrate coherent and non-coherent architectures, and optimize bandwidth, latency, power, and performance. Collaborate with customers and multidisciplinary hardware, software, firmware, physical design, and platform teams while guiding workload analysis, performance modeling, and end-to-end system solutions.

Owns secure semiconductor manufacturing test and provisioning on Advantest 93K ATE. Responsibilities include test architecture, SmarTest program development, first-silicon bring-up, characterization, HSIO and structural test integration, hardware coordination, silicon and ATE debug, production release, OSAT deployment, yield improvement, and high-volume manufacturing readiness.

Owns ATE test enablement, first-silicon bring-up, characterization, debugging, and production release for complex SoCs on Advantest 93K. Develops SmarTest programs, test methods, patterns, flows, binning strategies, and production content across wafer sort, final test, SLT, OSAT, and HVM. Leads ATE hardware readiness, HSIO validation, correlation, yield debugging, and cross-functional execution with design, DFT, firmware, vendors, contractors, and manufacturing partners.

Leads SoC power analysis, modeling, optimization, and pre- and post-silicon power convergence. Manages and mentors power engineers while collaborating with architecture, design, verification, and product teams. Defines power methodologies, workflows, budgets, and sign-off processes; develops workload scenarios; improves accuracy and silicon correlation; and drives performance-per-watt targets throughout the SoC lifecycle.

Lead the vision, requirements, roadmap, and delivery priorities for Arm’s multi-generation SoC firmware supporting infrastructure and AI systems. Engage customers, partners, architects, and engineering leaders to translate deployment needs into product requirements. Balance customer demands, technical constraints, schedules, and long-term strategy while driving delivery across global teams. Support go-to-market activities through customer engagements, sales discussions, technical presentations, and internal training.

Staff Design Engineer role at Arm with a stated annual salary range of $198,100 to $268,000. The provided description contains company values, hybrid-work information, application guidance, accommodations, and equal-opportunity statements, but does not specify technical responsibilities, required qualifications, technologies, travel, or clearance requirements.

Build and operate scalable platform services and APIs that improve engineering workflows. Develop Kubernetes operators, automate self-service capabilities, provision cloud infrastructure with Terraform, and manage reliable workloads using AWS, Docker, Kubernetes, Helm, and ArgoCD. Lead technical initiatives, apply secure software engineering practices, support production systems, and participate in an on-call rotation while collaborating across engineering teams.

Define performance telemetry and profiling architecture for next-generation Arm platforms spanning CPUs, accelerators, memory, interconnects, I/O, networking, storage, and chiplets. Establish observability specifications, telemetry models, profiling hooks, and cross-layer data flows from silicon through software and developer tools. Collaborate with hardware, software, power, modeling, and tooling teams to support workload analysis, bottleneck detection, performance validation, power-performance optimization, silicon bring-up, and deployment debugging across AI, edge, automotive, robotics, and infrastructure systems.

Lead performance architecture for next-generation server platforms by analyzing production silicon, AI and HPC workloads, microbenchmarks, cache and memory systems, and high-performance I/O. Define metrics and benchmarking strategies, identify bottlenecks, recommend optimizations, and translate workload and silicon insights into architectural improvements. Collaborate with hardware and software teams while providing technical leadership across complex system-design efforts.