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The role is accountable for strategic security leadership across semiconductor engineering environments, guiding teams in security practices while ensuring business efficiency.

Design and define high-speed on-chip interconnect architectures (coherent and non-coherent) including PCIe, CXL, and UA Link for scalable SoCs. Lead roadmap and early customer architecture engagements, collaborate with performance, power, physical design, software and firmware teams, and perform workload analysis and performance modeling to meet compute, memory, and interconnect targets.

Define and evaluate next-generation CPU microarchitectures for Cortex-X and Neoverse, develop performance models and simulations, analyze workloads, estimate performance/power/area trade-offs, collaborate with design teams and partners, and mentor junior engineers.

Customer-facing technical lead for platform firmware bring-up and debug across silicon, firmware, and OS layers. Support reference and custom platforms, debug DDR/PCIe and multi-socket issues, drive triage and root-cause analysis with internal teams, deliver workshops and documentation, and enable partners to accelerate platform readiness.

Lead end-to-end ATE secure provisioning for semiconductor manufacturing: define and implement fuse programming and lifecycle transitions, develop/validate Advantest 93K test methods, ensure secure boot and device identity, coordinate with Design/DV/Firmware/Security/Manufacturing, and define production controls, traceability, and guardrails across wafer sort, final test, SLT, and HVM.

As a SoC Emulation Engineer, you'll develop verification testbenches, modify RTL for SoC, and collaborate to define future architectures.

Drive hardware-aware ML algorithm development and optimization for ARM compute platforms. Analyze ML workloads (PPA focus), prototype algorithms, and optimize state-of-the-art networks for CPU/GPU/NPU targets.

As a Performance Analysis Engineer, you will analyze SoC performance, identify bottlenecks, collaborate with architects, and develop testing workflows.

Lead architecture, design, and delivery of coherent and non-coherent SoC interconnect fabrics. Define topology, QoS, latency, bandwidth, and power strategies; drive performance modeling, RTL microarchitecture and verification, debug system-level issues, mentor engineers, and plan interconnect roadmaps while collaborating with CPU/GPU/NPU/memory teams.

Develop and execute verification plans and testbenches (UVM/SystemVerilog/C) for Security IP and embedded processor subsystems. Verify cryptography, secure boot, key management, and multi-clock/multi-power domain IP; debug failures, improve verification methodology, and mentor teammates toward product sign-off.