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Develop and analyze memory controller IP and system performance models for Arm-based SoCs. Optimize power, performance, and microarchitecture using workload analysis, simulation, and emulation. Create performance methodologies, identify system bottlenecks, guide internal teams and partners, correlate models with RTL, and mentor engineers. Requires strong computer architecture expertise, C++ development, scripting, and experience with memory or interconnect performance modeling.

Senior SoC Verification Engineer role at Arm. The provided posting contains salary and company policy information but no detailed responsibilities or qualification requirements.

Architects, implements, and validates design-for-test techniques for Arm SoCs and subsystems. Responsibilities include DFT insertion, RTL and gate-level simulation, ATPG pattern generation, coverage debugging, DFT timing analysis, scan insertion, timing closure, ATE test validation, silicon debug, and characterization. The role collaborates with RTL, verification, physical implementation, test, and product engineering teams throughout development and tape-out.

Lead full-chip and block-level timing closure for complex SoCs across project lifecycle. Define and manage timing constraints, collaborate with cross-functional teams and EDA vendors, perform ECOs, address timing for multiple power domains and advanced nodes (5nm/3nm), and automate flows using scripting.

Design and validate custom memory circuits for Arm CPUs, GPUs, and SoCs using advanced semiconductor processes. Responsibilities include memory architecture, transistor-level circuit design, layout collaboration, performance-power-area optimization, design margining, physical verification, characterization, front-end verification, release procedures, and quality assurance. The role also involves improving design methodologies and using AI-assisted scripting to increase efficiency and quality.

Lead GPU architecture research and prototyping, collaborate with engineers to develop and validate architectural improvements, perform workload performance analysis (gaming and GPGPU), engage with product teams, and deliver world-class GPU IP through hands-on prototyping and experimental investigations.

Lead cross-functional product engineering for SoC/CPU/GPU manufacturability from pre-silicon readiness through post-silicon bring-up. Own manufacturing flow, ATE/SLT test and correlation, yield improvement, silicon/package reliability qualification, PVTF characterization, and failure analysis while coordinating with foundries, OSATs, design, validation, test, and quality. Support NPI/HVM readiness and audits, with international travel up to 20%.

Lead system-level definition and partner engagements to drive Arm AGI CPU adoption in cloud and data-center markets. Define rack-scale hardware solutions, collaborate with SoC, platform, software, and verification teams, support product requirements, perform competitive analysis, and represent Arm at industry forums to enable scalable, power-efficient server and accelerator deployments.

Lead microarchitecture, RTL development, and integration of high-speed interconnect subsystems (PCIe, CXL, UALink). Translate requirements into synthesizable RTL, collaborate across architecture, verification, firmware, and physical design, analyze traffic and buffering tradeoffs, drive delivery from concept through synthesis and timing closure, mentor engineers, and debug cross-functional issues to meet performance, power, area, and reliability targets.

Lead the development of next-generation system architectures, drive technology objectives, and collaborate with teams to ensure alignment in product goals.