Top Tech Jobs & Startup Jobs in Austin, TX

One Month AgoSaved
In-Office
Austin, TX, USA
Senior level
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Execute synthesis, place and route, static timing analysis, and physical verification for ASIC partitions. Collaborate with architecture, RTL, DFT, and methodology teams to resolve implementation and signoff issues, close EM/IR, drive LEC, and improve physical design flows. Troubleshoot EDA workflows, work with vendors, implement low-power techniques, and develop custom TCL scripts for Cadence and Synopsys tools. The role is fully onsite in San Jose, California.
Top Skills: AsicCadenceEdaElectromigration And Ir AnalysisInnovusLogical Equivalence CheckingPhysical VerificationPlace And RoutePower Delivery NetworksQuantusSocStatic Timing AnalysisSynopsysSynthesisTclTempus
Reposted 3 Months AgoSaved
In-Office
Austin, TX, USA
Senior level
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Perform synthesis, place-and-route (PnR), static timing analysis (STA) and signoff for ASIC partitions. Collaborate with architects, RTL and DFT teams to close timing, EM/IR and LEC issues, refine physical design methodologies, troubleshoot flows, and coordinate with EDA vendors to meet tight schedules and design goals.
Top Skills: CadenceElectromigration/Ir (Em/Ir)InnovusLogical Equivalence Checking (Lec)Physical VerificationPlace And RoutePower Delivery Network (Pdn)QuantusSoc DesignStatic Timing AnalysisSub-7NmSynopsysSynthesisTclTempus
Reposted 10 Days AgoSaved
Remote
2 Locations
Senior level
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Integrates first-party and third-party IP into subsystems and SoCs using Verilog and SystemVerilog. Performs synthesis, timing constraint development, floor-planning analysis, performance optimization, register integration, and design-quality closure through CDC, lint, and RDC checks. Communicates project progress to customers, supports process improvements, resolves complex problems independently, and provides informal guidance to junior staff.
Top Skills: Clock Domain Crossing (Cdc)Floor PlanningIp IntegrationLintReset Domain Crossing (Rdc)RtlSoc IntegrationSynthesisSystemverilogTiming ConstraintsVerilog
22 Days AgoSaved
Remote
Texas, USA
Senior level
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Designs physical silicon layouts for high-speed analog and mixed-signal circuits, including SerDes, ADCs, DACs, PLLs, and other advanced blocks. Responsibilities include floor planning, hierarchical integration, package-aware co-design, parasitic and noise control, device matching, shielding, and reliability verification. The role requires hands-on custom IC layout experience with advanced CMOS or FinFET nodes, especially TSMC N3, N5, or N7, along with DRC, LVS, ERC, antenna, EM/IR, and ESD closure.
Top Skills: AdcCmosDacDrcEm/IrErcEsdFinfetLvsMicro-BumpPackage-Aware Co-DesignPllSerdes
2 Months AgoSaved
Remote
Texas, USA
92K-152K Annually
Senior level
92K-152K Annually
Senior level
Cloud • Enterprise Web • Hardware • Information Technology • Internet of Things • Robotics • Semiconductor
Leads a large inside sales support or production operations team, coordinating daily activities, setting priorities, managing resources, and collaborating with supervisors. Coaches employees, conducts performance evaluations, recommends pay actions, resolves complex problems, and contributes to policy and resource planning. The role is hybrid, with three days in the office and two days remote.
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