Top Tech Jobs & Startup Jobs in Austin, TX

Owns architecture, microarchitecture, RTL design, integration, and implementation of high-speed I/O and memory subsystems for AI accelerator platforms. Responsibilities include SystemVerilog development, front-end design flows, protocol and vendor IP integration, PPA optimization, timing closure, verification collaboration, issue resolution, and cross-functional lifecycle execution from architecture through silicon.

Own full lifecycle recruiting for semiconductor hardware engineering roles, including design verification, ASIC/RTL design, physical design, and PCB/systems engineering. Partner with hiring managers to define roles, build pipelines, design interviews, source passive silicon talent, coordinate feedback, close candidates, and maintain recruiting data and metrics in Greenhouse.

Lead development and optimization of the compiler stack for ML systems, collaborate across teams, integrate and deploy products, map ML operations to hardware, and drive compiler infrastructure innovation and performance debugging.

Own and operate a global AI inferencing platform: ensure uptime, low-latency performance, scalability and cost efficiency. Build monitoring, alerting, CI/CD, IaC, autoscaling, capacity planning, incident response, and participate in a shared on-call rotation to maintain 24/7 service reliability.

Design and implement RTL components for AI accelerator ASICs from microarchitecture through tape-out and silicon bring-up. Responsibilities include writing and debugging SystemVerilog, optimizing power, performance, and area, supporting synthesis and timing closure, and applying lint, CDC, LEC, and assertion-based quality checks. The engineer collaborates with architecture, verification, and physical design teams while contributing to compute datapath, on-chip network, and memory subsystems.

Own microarchitecture and synthesizable SystemVerilog RTL for major AI accelerator blocks from specification through tape-out. Drive power, performance, and area optimization, timing closure, synthesis, STA, lint, CDC, LEC, assertions, and verification collaboration. Partner with architecture and software teams on performance improvements, advance EDA automation, lead design reviews, and mentor engineers.

Design and implement block- and SoC-level DFT architectures for complex AI accelerator chips. Develop ATPG, MBIST, scan, JTAG, IEEE 1500, and IJTAG infrastructure; automate insertion, pattern generation, coverage analysis, and debug; support DFT timing closure, ATE deployment, silicon bring-up, diagnosis, failure localization, yield analysis, and manufacturing test optimization.

As a Senior Cloud SRE, you'll ensure the reliability and performance of our AI inferencing service, handle incident management, and optimize cloud infrastructure and resource utilization.

Design and own RTL hardware blocks for AI accelerator ASICs through microarchitecture, implementation, tapeout, and silicon bring-up. Develop high-performance SystemVerilog designs, meet power, performance, and area targets, and collaborate with verification and physical design teams. Implement assertions and run lint, CDC, LEC, synthesis, and timing flows. Support design reviews, post-silicon debugging, and improvements to ASIC design methodologies, including AI and automation in EDA workflows.

Define and own networking architecture for next-generation super-pod ML hardware. Lead R&D, specify high-performance networking fabrics, drive ML networking roadmap, collaborate cross-functionally across silicon, systems, and software, contribute to industry standards, and deliver performant, reliable, and secure interconnect solutions at scale.