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Participate in mixed-signal ASIC verification: plan verification, develop UVM testbenches, implement functional verification, create constrained-random tests, perform failure and coverage analysis, support gate-simulations, regression debug, and verification infrastructure improvements.

Lead and execute block- and chip-level functional verification for mixed-signal ASICs. Develop verification plans, testbenches, constraint-random and directed tests, coverage closure, regression triage, gate-level simulation analysis, and collaborate with cross-functional teams for pre- and post-silicon validation.

Act as the voice of the customer for quality across multiple accounts, drive issue resolution and corrective actions, monitor performance trends, collaborate cross-functionally, and support product qualification and reliability improvements.

Support customers integrating Class D amplifiers, design reference platforms and PCBs, author application documents, build Python automation for audio characterization, perform circuit analysis and measurements, and contribute product insights while collaborating cross-functionally. Occasional (~2 weeks/year) travel for customer support.