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Own block- and subsystem-level physical design from RTL synthesis through GDSII sign-off. Perform floorplanning, placement, CTS, routing, timing closure, sign-off (EM/IR/RC/DRC/LVS), generate abstracts for hierarchical integration, improve PPA with RTL collaboration, and supervise third-party delivery.

The Physical Design Engineer will focus on block-level implementation, timing closure, PPA optimization, and supervising outsourced design work while improving design flows.

As a Design Verification Engineer, you will create and maintain UVM/SystemVerilog testbenches, execute verification plans, debug issues, and collaborate with cross-functional teams to ensure IP functionality and performance.

As a Design Verification Engineer, you will collaborate with architects and RTL designers to verify designs, develop test plans and infrastructure, ensure performance, and debug issues across the hardware-software stack.

Co-develop cutting-edge software for AI applications, focusing on low-level drivers and high-level frameworks, while optimizing performance for large transformer models.

The Design Verification Engineer will lead IP subsystem verification, develop UVM/SystemVerilog environments, and collaborate with cross-functional teams to validate hardware-software performance.