Top Tech Jobs & Startup Jobs in Austin, TX

Designs, develops, and maintains SAP test automation solutions using Worksoft and Java. Automates SAP and non-SAP business processes, validations, and integrations across SAP S/4HANA environments. Builds AI/GenAI-powered automation with LLM integrations and agent-based workflows. Supports CI/CD, Git, SQL, Agile delivery, enterprise integration, stakeholder collaboration, and quality standards. Requires strong SAP SD expertise, SAP MM/FI exposure, and at least five years of test automation experience.

Lead AI-assisted software engineering across the SDLC, design and implement large-scale C#/.NET microservices, deploy LLMs and ML models to production, modernize legacy systems to cloud-native architectures, work with containers, CI/CD and databases (MongoDB/Aerospike/Postgres), and mentor engineers while establishing AI-assisted development practices and documentation.

Serve as a functional SME for Oracle Fusion Cloud Finance, configuring, troubleshooting, and supporting Accounts Receivable, Accounting, Advanced Collections, and Enterprise Contracts. Translate business requirements into solutions, support implementations and production environments, troubleshoot PaaS integrations, and collaborate with technical, functional, and client teams. Gather requirements, design solutions, test, resolve issues, document processes, and manage stakeholder communications. Staffing domain experience and extensive Oracle Cloud Finance expertise are required.

Provides functional leadership and subject-matter expertise for Oracle Cloud Finance implementations and optimizations. Responsibilities include configuring and troubleshooting Oracle Fusion Finance modules, translating client requirements into solutions, resolving Oracle Cloud and PaaS issues, managing client relationships, delivering project milestones, and integrating staffing workflows with Oracle Cloud Finance.

Remote 12-month contract RTL Design Engineer to own micro-architecture and RTL implementation for complex digital blocks. Requires SystemVerilog/Verilog expertise, memory controller and SoC integration experience, IP integration, multi-clock-domain design, and sign-off familiarity (CDC/RDC/lint/synthesis). Works independently and collaborates with DV for closure and debug.