Develop system-level performance models and simulation frameworks for AI workloads, software runtimes, and hardware architectures. Model SoC components, memory systems, and interconnects; analyze bottlenecks and architectural tradeoffs; and evaluate latency, throughput, scalability, and energy efficiency. Collaborate with hardware architects, software engineers, and ML teams to support hardware-software co-design and guide next-generation AI compute platform decisions.

Develop and execute verification strategies for a next-generation Physical AI SoC. Build SystemVerilog and UVM environments, assertions, checkers, scoreboards, and formal verification flows. Verify digital blocks, memory systems, interconnects, processors, DMA engines, and complete HW/SW behavior. Perform performance, latency, QoS, emulation, FPGA prototyping, pre-silicon bring-up, post-silicon debugging, and hardware-software root-cause analysis.

Designs and evaluates AI model architectures for efficient hardware implementation. The role analyzes transformers and other models, translates computation graphs into hardware dataflows, develops performance and efficiency models, and collaborates across machine learning, software, and hardware teams. Responsibilities include optimizing models for specialized platforms and identifying opportunities for hardware-software co-design in cloud, edge, robotics, autonomous systems, and Physical AI.