Top Tech Jobs & Startup Jobs in Austin, TX

Lead go-to-market strategy for AI-powered networking use cases across Cisco Networking. Curate and prioritize use cases, synthesize cross-portfolio intelligence, define GTM and messaging, engage customers and analysts, align stakeholders, and drive adoption from early availability to general availability.

Lead global strategy, execution, and business performance for Cisco Live across AMERICAS, EMEA, and APJC. Manage a distributed team, define multi-year roadmap, ensure brand consistency, drive OKRs and pipeline growth, integrate product launches and acquisitions, and deliver large-scale, data-driven conference experiences with operational excellence and international travel.

Serve as the SLED point of contact for legal financing agreement preparation and partner funding. Perform contract due diligence and execution, manage SLED contract operations (state and national), support E-Rate operations, ensure partner compliance, build transactions in lease/loan systems, train sales on bid tools, support audits and forecasting, and drive process improvements and SLED projects across cross-functional teams.

Perform RTL-to-GDSII physical implementation including synthesis, hierarchical floorplanning, place-and-route, STA, power integrity, CTS, timing ECOs and equivalence checks. Improve EDA tool flows, collaborate with RTL/DFT/EDA vendors, and contribute automation for STA and sign-off across multi-mode/multi-corner scenarios.

Lead cross-functional initiatives to assess and improve product lifecycle management (PLM), NPI, sustaining, and supply chain processes. Define future-state PLM strategies, analyze data to identify improvements, mitigate risks, drive change management, and facilitate design-thinking sessions to align stakeholders and deliver scalable operational improvements.

Develop and maintain STA and extraction flows, ensure convergence and correlation between PNR, Spice, and STA, create methodologies, guidelines, and checklists, resolve design and flow issues, and drive execution while collaborating with Physical Design.

Lead DFT solutions for next-generation ASICs: define and implement SSN and hierarchical DFT architectures, perform scan insertion and ATPG (stuck-at, transition, cell-aware, path delay), run gate-level SDF simulations, integrate/verify DFT IP, support post-silicon debug and diagnosis, and automate test flows using Python/Tcl/C++.

Lead RTL-to-GDSII implementation for advanced-node ASICs (sub-7nm to 2nm). Perform hierarchical floorplanning, place-and-route, clock and power distribution, STA and timing closure, develop automation scripts, collaborate with RTL/DFT teams to debug physical issues, implement ECO strategies, support sign-off and physical verification, and deliver assigned blocks through tapeout.

Design, validate, bring-up, and debug enterprise switching hardware for the Catalyst 9300 series. Drive manufacturability, reliability, and cost decisions; collaborate with cross-functional teams on signal integrity, power, thermal, EMI/EMC, compliance, manufacturing readiness, and sustaining support.