Top Tech Jobs & Startup Jobs in Austin, TX

The role involves bridging architecture and design, analyzing power trade-offs, and improving power efficiency for CPU cores, with a focus on AI and HPC workloads.

Design and optimize power-efficient ASIC, GPU, and processor hardware for mobile, embedded, and datacenter platforms. Develop power metrics, drive power reductions, and deliver verified RTL meeting performance, area, and power targets. Collaborate with architects, designers, verification engineers, and VLSI teams on high-performance designs.

Develop CUTLASS platform components for Tensor Core operations, GPU synchronization, scheduling, and hardware features using CUDA C++ and Python. Advance the MLIR-based compiler backend through dialect and compiler pass development. Create high-performance example kernels and collaborate with GPU architecture, CUDA, and compiler teams on future hardware programming models and performance.

Benchmark and optimize deep learning model inference and training performance on NVIDIA GPUs. Develop tooling for automated benchmarking, analysis, and performance optimization of CUTLASS kernels. Identify gaps between theoretical and realized performance, recommend software or model improvements, and serve as the team’s kernel-performance authority across GPU architecture, deep learning frameworks, and QA teams.

Design and implement high-performance, area- and power-efficient RTL blocks for NVLink Fusion AI infrastructure SoCs. Responsibilities include architectural analysis, microarchitecture specification, RTL development, verification, synthesis and timing closure, IP selection and integration, and collaboration with architecture, verification, formal verification, and SoC integration teams.

Develop and invent parallel, graph-based RTL analysis and optimization methods. Analyze RTL impacts on latency, power, DFT, clocking, and power delivery. Explore ML (LLMs, GNNs, GANs, RL) and high-performance algorithms for logic synthesis, clustering, and implementation. Drive end-to-end tool development and collaborate with design teams to deploy optimizations.

Lead technical vision and strategy for next-generation graphics developer tools. Design and prototype tooling, drive cross-team initiatives, mentor engineers, engage external developers and partners, and deliver production-ready solutions that improve graphics development, debugging, profiling, and optimization workflows.

Design and deliver high-performance, area- and power-efficient ASIC/GPU micro-architecture and RTL. Develop agentic AI solutions to craft micro-architecture, implement RTL, and produce fully verified, synthesis/timing-clean designs. Collaborate with designers and tool owners, and build LLM-powered engineering assistants, multi-agent systems, and multi-modal dialogue tools to accelerate chip design workflows.

Develop and deliver system-level IP and RTL to measure performance on GPUs/SOCs. Create and automate flows, run/debug RTL checks (CDC, clocks, resets, latency), implement RTL features, and collaborate with architects, designers, and software engineers to support projects and performance monitoring.

Lead floorplan design from early architecture through physical implementation for high-performance SoCs/CPUs/GPUs. Collaborate with cross-functional teams to optimize area, power, timing, and interconnect; develop AI-driven workflows and tools; identify technical risks and drive mitigation to meet product goals.