Top Tech Jobs & Startup Jobs in Austin, TX

The intern will develop a flow to monitor design health metrics and implement automated fixes while collaborating with foundry partners.

Lead the development of advanced packaging and 3DIC analysis flows. Requires extensive experience in signal integrity and power integrity related to IC and PCB design, as well as customer interaction. Must have strong knowledge of Cadence tools and advanced packaging concepts.

The Server Farm Engineer will manage and enhance a high-performance compute environment, collaborate with R&D teams, and develop strategies for operational excellence across multiple locations.

The Sr IP Sales Executive is responsible for developing and driving a sales pipeline for Design IP technology, managing multi-functional teams, and achieving sales targets through strategic selling and market feedback.

Develop bare-metal firmware in C for DDR5 PHY using microcontrollers; implement low-level APIs and training algorithms; collaborate with hardware designers and verification teams for firmware-hardware co-verification; debug in RTL (C+Verilog) simulations and on silicon bring-up; use scripting and EDA tools for verification and diagnostics.

Lead global account strategy and execution to grow Cadence EDA, Design Services, HW, and IP revenue. Build C-level relationships, manage complex multimillion-dollar deals, maintain pipeline, and coordinate cross-functional resources to exceed bookings and market-share targets.

The Sr IP Sales Executive will build and manage a sales pipeline for Design IP technology, drive market penetration, and achieve sales targets by collaborating with various teams and executing strategic sales plans.

Lead verification projects at subsystem/SOC level, develop testbenches, mentor engineers, and ensure metric-driven quality verification processes.

The role involves SoC/ASIC Digital Design focusing on DFT, requiring expertise in scan insertion, ATPG, and collaboration with cross-functional teams.

The role involves collaborating with R&D and Application Engineering teams to enhance chip design tools, focusing on PPA benchmarking and optimization.