Top Tech Jobs & Startup Jobs in Austin, TX

Develops AI and deep learning models for electrothermal, electromagnetic, and structural simulations. Leads research on generalization and interpretability of large models in complex physics scenarios, monitors emerging AI advances, and integrates research into products to improve simulation accuracy and performance. Requires strong experience with deep learning frameworks, generative models, programming in Python and C/C++, and relevant graduate education.

Supports Cadence product adoption and customer RTL-to-GDSII implementation projects. Performs synthesis, place and route, clock tree synthesis, static timing analysis, low-power and multi-voltage implementation, timing debugging, tapeout support, and full-flow methodology development. Leads customer evaluations, competitive benchmarks, technical presentations, and implementation services across advanced technology nodes for complex CPU, GPU, DSP, wireless, and mobile designs.

Provides pre-sales and post-sales technical support for Cadence digital implementation and signoff tools. Delivers customer workshops, benchmarks, demonstrations, methodology consultations, technical evaluations, and product support. Partners with sales teams on technical campaigns, supports customer implementations and usage expansion, collaborates with R&D on methodology improvements, and creates technical content. Requires expertise in digital design, semiconductor fundamentals, static timing analysis, ASIC implementation flows, scripting, and customer-facing problem solving.

Manage Cadence’s academic programs, university partnerships, student innovation initiatives, and workforce development activities. Lead program timelines, budgets, documentation, communications, dashboards, reporting, onboarding, and engagement across key universities. Develop marketing content and communication strategies, coordinate conferences and academic events, support speakers and participants, and track participation, outreach, and program outcomes. Partner with Corporate Marketing and internal stakeholders to expand Cadence’s academic ecosystem and promote emerging technologies such as Physical AI and semiconductor design.

Develop and optimize high-performance, multi-threaded software for physical synthesis and routing in digital IC design. Responsibilities include algorithm research, C/C++ development on Linux, distributed-system debugging, performance optimization, and collaboration with global R&D and product engineering teams. The role supports advanced semiconductor design flows and may involve GPU programming, scripting automation, timing analysis, and EDA tools.

Develops, enhances, tests, troubleshoots, and documents software throughout the development lifecycle. Reviews code, resolves defects, translates technical requirements into scalable solutions, and contributes to system architecture and development-process improvements. Requires substantial C++ experience, desktop engineering and OpenGL expertise, computational geometry knowledge, cross-platform development experience, and the ability to handle ITAR-controlled data. Relocation to Austin, Texas may be required.

Leads customer and partner engagements for Cadence timing signoff and closure solutions across advanced semiconductor nodes. Drives STA, IR Drop, power and timing closure benchmarks, flow optimization, tool adoption, and methodology deployment. Collaborates with R&D and product engineering, influences tool enhancements, leads technical programs, and represents Cadence through industry presentations and technical publications. Requires deep advanced-node signoff expertise, scripting skills, customer leadership, and familiarity with Cadence EDA tools.

Entry-level rotational application engineering role for new STEM bachelor’s graduates. Provides customer-facing design services, technical sales support, and troubleshooting for Cadence EDA tools. The one-year program includes rotations across digital, physical, analog, package, systems, verification, and emulation design, with training in HDLs, synthesis, UNIX, programming, scripting, and silicon analysis. Graduates transition into a permanent CST business group based on interests and company needs.

Leads front-end semiconductor design projects and mentors RTL engineers. Defines microarchitecture, develops and optimizes RTL in Verilog, SystemVerilog, or VHDL, and oversees pre-silicon verification, lint, CDC, formal verification, synthesis, and signoff. Collaborates with design verification, physical design, architecture, and firmware teams to deliver IPs and SoCs meeting PPA goals. Supports SDC creation, physical design, and static timing analysis teams.

Leads physical design and DFT teams delivering advanced-node SoCs from RTL or netlist through GDS. Owns customer engagements, technical decisions, PPA optimization, timing and power closure, foundry and library selection, sign-off criteria, and schedule execution. Collaborates with RTL, synthesis, CAD, library, tools R&D, and customer teams while improving methodologies, AI adoption, and best practices. Requires deep expertise in digital implementation flows, backend EDA tools, advanced semiconductor nodes, scripting, and customer-facing technical leadership.