Top Tech Jobs & Startup Jobs in Austin, TX

Architects and designs processor core logic enhancements in partnership with the Chief Architect. Collaborates with validation and physical design teams to productize solutions, focusing on areas such as load/store, instruction fetch, branch prediction, memory management, and bus protocols. The role may also analyze performance bottlenecks, model improvements, and implement optimization solutions.

Supports Cadence digital implementation and signoff products by debugging customer issues, partnering with R&D and release teams, running design benchmarks, and developing implementation flows. Requires deep expertise in ASIC RTL-to-GDSII methodologies, timing closure, PPA optimization, physical design, low-power and hierarchical design, and industry-standard EDA tools. The role also involves automation using Perl, Tcl, and shell scripting.

Support Cadence Conformal products, especially equivalency checking, by troubleshooting customer issues, debugging systematically, identifying workarounds, and translating findings for R&D. Collaborate with customers and R&D on product features, enhancements, and solutions. Apply RTL synthesis and verification knowledge, scripting skills in Tcl and Perl, technical writing, and strong communication to meet deadlines and resolve ambiguous problems.

Leads a processor design verification team responsible for verifying microprocessor cores and peripherals. Develops verification plans, simulation and emulation testbenches, diagnostics, assertions, coverage monitors, and automated verification flows. Drives coverage closure, collaborates with design, architecture, firmware, and verification teams, and manages work reporting for 7–10 engineers. Requires deep CPU architecture, SystemVerilog, UVM, gate-level simulation, assembly programming, and design verification leadership experience.

Lead architecture, development, and execution for Conformal logical equivalence checking and ECO technologies. Drive formal verification, scalability, performance, quality, debugging, and AI-powered innovation. Guide complex technical initiatives, resolve customer escalations, influence product strategy, collaborate across engineering and product teams, mentor senior engineers, and engage strategic semiconductor customers and partners.

Manage digital implementation and signoff customer engagements, providing expert guidance on physical implementation, verification flows, process technology enablement, and PPA optimization. Conduct benchmarks, solve complex customer issues, test and deploy solutions, and define product enhancements with R&D, field engineers, customers, and foundries. Provide technical leadership, presentations, documentation, and mentorship while supporting projects at domestic and international sites.

Build and manage sales pipelines for Design IP technology across North American accounts. Drive market penetration, adoption, revenue, and strategic sales plans while managing complex $1M+ licensing deals. Collaborate with engineering, marketing, legal, finance, executives, and EDA sales teams. Develop customer relationships from startups to enterprises, articulate IP value propositions, negotiate contracts, meet revenue targets, and provide market feedback to product leadership.

Lead digital design engineer responsible for designing and integrating SoC IPs, developing microarchitectural specifications, performing lint, CDC, synthesis, and PPA optimization, and supporting verification and physical design teams. The role also involves creating synthesis constraints, debugging design issues, automating repetitive tasks with scripting, and collaborating across engineering teams.

Design and integrate SoC IPs from architectural specifications; perform Lint and CDC checks; develop synthesis constraints and optimize power, performance, and area. Create microarchitectural specifications, support verification and physical design teams, and automate repetitive tasks using scripting. Collaborate across teams to execute projects effectively.

Leads advanced semiconductor signoff methodology development, customer enablement, product deployment, and technical investigations for timing, power, signal integrity, ECO closure, and physical implementation. Collaborates with customers, R&D, and field engineering teams to resolve design closure challenges, qualify advanced-node flows, support tapeouts, validate product enhancements, and influence roadmap direction. Provides technical leadership for strategic engagements, customer escalations, methodology collateral, and engineering mentorship.