Top Tech Jobs & Startup Jobs in Austin, TX

Lead design of mmWave (30+ GHz) RF transceivers and components across full product lifecycle. Develop PAs, LNAs, mixers, VCOs, PLLs, and Tx/Rx chains; perform parasitic/EM/thermal modeling, layout and verification, tape-out, and lab validation. Engage with customers and use advanced EDA and EM tools on RF SOI processes.

Lead product and go-to-market strategy for Cadence digital and mixed-signal verification solutions. Partner with strategic accounts to define technical and commercial requirements, influence roadmap and packaging, enable field teams, and drive adoption and revenue across the customer lifecycle from evaluation to enterprise deployment. Lead cross-functional initiatives with Sales, Apps Engineering, and R&D and engage with executives to deliver measurable business outcomes.

Responsible for designing, developing, debugging, and supporting Design-for-Test software in VLSI Design Automation.

Lead product and business growth for Cadence digital and mixed-signal verification solutions by owning customer-facing strategy, market development, and go-to-market. Partner with strategic accounts to uncover technical and commercial pain points, shape product direction and packaging, build value propositions, and drive enterprise adoption. Lead cross-functional initiatives across Sales, Applications Engineering, and R&D, engage executives, and align teams to measurable outcomes across the full customer lifecycle.

The Technical Program Manager will oversee R&D projects and customer engagements, ensuring effective project execution, stakeholder communication, and team collaboration.

As a Software Engineer I, you will provide R&D support, engage in debugging, and develop new features to enhance product performance in a collaborative team environment.

Lead and execute complex digital implementation and signoff customer engagements. Provide expert guidance on physical implementation, verification, timing and power analysis, enable advanced-node process platforms, drive PPA realization, develop methodologies and flows, partner with R&D/FAEs/foundries, and manage and mentor a customer-facing engineering group.

Lead SoC/ASIC DFT activities including scan insertion, compression scan, LBIST/MBIST, and ATPG pattern generation. Verify and debug ATPG testbenches and failures, work with synthesis/Verilog testbenches, apply JTAG/IEEE standards, and collaborate across architecture, design, and customers to independently deliver DFT solutions using Cadence flows.

Develop and validate power integrity and PDN analysis methodologies for digital sign-off. Collaborate with R&D to build AI-driven IR mitigation, 3DIC and electrothermal optimization flows, support strategic customers, and drive multiphysics product engineering and solutions.

Lead the development of advanced packaging and 3DIC analysis flows. Requires extensive experience in signal integrity and power integrity related to IC and PCB design, as well as customer interaction. Must have strong knowledge of Cadence tools and advanced packaging concepts.