Top Tech Jobs & Startup Jobs in Austin, TX

Leads cross-functional teams delivering semiconductor services projects and technology initiatives from scoping through completion. Responsibilities include creating statements of work and cost plans, managing schedules, budgets, risks, resources, deliverables, customer communications, and commercial negotiations. The role partners with account, technical, finance, legal, sales, field, and services teams while driving customer satisfaction and process improvements. Occasional domestic and international travel is required.

Leads semiconductor design verification strategy and execution using UVM/SystemVerilog, constrained-random testing, formal verification, and gate-level simulation. Designs reusable testbenches, develops complex sequences, analyzes coverage, debugs design issues, and oversees verification sign-off. Mentors junior engineers, coordinates with design, architecture, and emulation teams, and manages verification schedules, risks, and priorities.

Lead design verification strategy and execution for customer ASIC projects. Architect reusable UVM/SystemVerilog testbenches, develop constrained-random tests, analyze coverage, perform formal verification and gate-level simulation, debug complex design issues, and provide verification sign-off. Mentor junior engineers, manage verification schedules and risks, and collaborate with design, architecture, emulation, and customers.

Lead verification strategy and architecture for semiconductor ASIC and SoC designs. Build reusable UVM/SystemVerilog testbenches, develop constrained-random tests, perform formal verification and gate-level simulation, analyze coverage, debug complex design issues, and approve verification sign-off. Mentor junior engineers, coordinate with design, architecture, and emulation teams, and manage verification schedules, risks, and priorities.

Leads design verification strategy and architecture for customer ASIC projects. Designs reusable UVM/SystemVerilog testbenches, develops constrained-random tests, manages coverage, performs formal verification and gate-level simulation, and debugs complex design issues. Provides technical leadership through customer interaction, sign-off approval, cross-functional collaboration, project scheduling, risk management, and mentorship of junior engineers.

Lead functional verification for Cadence memory controller IP. Develop and enhance UVM-based verification environments, create test plans, validate customer configurations through regression testing, analyze functional and code coverage, support customers using the environment, and ensure designs meet technical and quality requirements.

Architects and designs processor core logic enhancements in partnership with the Chief Architect. Collaborates with validation and physical design teams to productize solutions, focusing on areas such as load/store, instruction fetch, branch prediction, memory management, and bus protocols. The role may also analyze performance bottlenecks, model improvements, and implement optimization solutions.

Support Cadence Conformal products, especially equivalency checking, by troubleshooting customer issues, debugging systematically, identifying workarounds, and translating findings for R&D. Collaborate with customers and R&D on product features, enhancements, and solutions. Apply RTL synthesis and verification knowledge, scripting skills in Tcl and Perl, technical writing, and strong communication to meet deadlines and resolve ambiguous problems.

Leads a processor design verification team responsible for verifying microprocessor cores and peripherals. Develops verification plans, simulation and emulation testbenches, diagnostics, assertions, coverage monitors, and automated verification flows. Drives coverage closure, collaborates with design, architecture, firmware, and verification teams, and manages work reporting for 7–10 engineers. Requires deep CPU architecture, SystemVerilog, UVM, gate-level simulation, assembly programming, and design verification leadership experience.

Lead architecture, development, and execution for Conformal logical equivalence checking and ECO technologies. Drive formal verification, scalability, performance, quality, debugging, and AI-powered innovation. Guide complex technical initiatives, resolve customer escalations, influence product strategy, collaborate across engineering and product teams, mentor senior engineers, and engage strategic semiconductor customers and partners.