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Develop bare-metal firmware in C for DDR5 PHY using microcontrollers; implement low-level APIs and training algorithms; collaborate with hardware designers and verification teams for firmware-hardware co-verification; debug in RTL (C+Verilog) simulations and on silicon bring-up; use scripting and EDA tools for verification and diagnostics.

Lead verification projects at subsystem/SOC level, develop testbenches, mentor engineers, and ensure metric-driven quality verification processes.

The role involves collaborating with R&D and Application Engineering teams to enhance chip design tools, focusing on PPA benchmarking and optimization.

Lead strategic co-selling, marketing and communications partnerships with Tier 1 ecosystem partners to grow joint business and channels. Develop partner programs, campaigns, events, and collateral; align executives and sales through training; generate qualified leads and product opportunities; nurture long-term relationships; track and report program performance and ROI.

Develop and debug bare-metal C firmware for DDR5 PHY on microcontrollers, collaborate with hardware designers and verification teams to implement training algorithms, perform RTL and silicon bring-up debugging, and use scripting and EDA tools for co-verification and simulation.

Develop and debug bare-metal firmware for DDR5 PHY microcontrollers, collaborate with hardware designers and verification teams to implement training algorithms, perform firmware-hardware co-verification in RTL simulations, and support silicon bring-up and debugging using EDA tools and scripting.

Design-for-Test (DFT) engineer responsible for scan chain and compression insertion, MBIST/LBIST, ATPG pattern generation and verification, debugging failures, verifying ATPG testbenches, and collaborating across architecture, design, and customer teams. Work with JTAG/IEEE test standards and Cadence flows to meet test coverage and quality metrics.

Serve as a technical pre-sales leader, driving cross-functional campaigns that match Cadence digital design and EDA solutions to customer needs. Build relationships with customer engineering and leadership, influence buying decisions, manage complex technical projects, and support multi-million-dollar sales through technical expertise across the RTL-to-GDSII flow and AI/ML optimization methods.

Lead design of mmWave (30+ GHz) RF transceivers and components across full product lifecycle. Develop PAs, LNAs, mixers, VCOs, PLLs, and Tx/Rx chains; perform parasitic/EM/thermal modeling, layout and verification, tape-out, and lab validation. Engage with customers and use advanced EDA and EM tools on RF SOI processes.

Responsible for designing, developing, debugging, and supporting Design-for-Test software in VLSI Design Automation.