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The Senior Principal Design Engineer supports Cadence product adoption, focusing on ASIC design and methodology improvement, while managing customer evaluations and performing design automation scripting.

Develop bare-metal firmware in C for DDR5 PHY using microcontrollers; implement low-level APIs and training algorithms; collaborate with hardware designers and verification teams for firmware-hardware co-verification; debug in RTL (C+Verilog) simulations and on silicon bring-up; use scripting and EDA tools for verification and diagnostics.

Lead verification projects at subsystem/SOC level, develop testbenches, mentor engineers, and ensure metric-driven quality verification processes.

Lead Front End Design projects, mentor a team of RTL design engineers, develop microarchitectures, and oversee verification activities in the semiconductor industry.

Lead Physical Design projects and teams while collaborating with customers to meet performance targets and deliver complex SoCs. Drive innovation and technical solutions at advanced nodes, ensuring design closure and optimizing for power, area, and performance.

The role involves collaborating with R&D and Application Engineering teams to enhance chip design tools, focusing on PPA benchmarking and optimization.

Lead strategic co-selling, marketing and communications partnerships with Tier 1 ecosystem partners to grow joint business and channels. Develop partner programs, campaigns, events, and collateral; align executives and sales through training; generate qualified leads and product opportunities; nurture long-term relationships; track and report program performance and ROI.

Entry-level, cohort-based rotational role providing front-line EDA application support, technical sales assistance, and design services. Work with customers and internal teams on digital/analog design, verification, simulation, physical design, timing/power/SI sign-off, embedded HW/SW co-verification, and hardware emulation. Two six-month technical rotations followed by placement in a CST business group.

Develop and debug bare-metal C firmware for DDR5 PHY on microcontrollers, collaborate with hardware designers and verification teams to implement training algorithms, perform RTL and silicon bring-up debugging, and use scripting and EDA tools for co-verification and simulation.

Develop and debug bare-metal firmware for DDR5 PHY microcontrollers, collaborate with hardware designers and verification teams to implement training algorithms, perform firmware-hardware co-verification in RTL simulations, and support silicon bring-up and debugging using EDA tools and scripting.