Top Tech Jobs & Startup Jobs in Austin, TX

The IP Verification Engineer will lead verification efforts for ASIC IP, build environments, mentor team members, and ensure designs meet specifications in 5G infrastructure.

Leads Ericsson Silicon’s EDA ecosystem strategy and horizontal technical program execution across global engineering teams. Responsibilities include EDA roadmap development, vendor partnerships, tool evaluations, SOW negotiations, license portfolio optimization, capacity planning, budget and total cost analysis, technology-node enablement, and cross-functional alignment. The role drives strategic build-versus-buy decisions, advanced-node flow enablement, AI/ML and cloud EDA adoption, and improvements in tool capability, cost efficiency, and environment readiness.

Design and own microarchitecture and RTL for L1 accelerators, translating DSP/FEC algorithms into high-performance SystemVerilog. Deliver end-to-end IP including specification, RTL, synthesis, timing closure, and hand-off. Lead verification, backend/physical design collaboration, and optimize power/area/throughput across major blocks.

Develop and execute ASIC and IP verification across block and top levels. Build UVM testbenches, TLM models, test plans, and randomized or directed tests; perform RTL debug and coverage closure; and verify hardware with embedded software. The role requires SystemVerilog, UVM, scripting, Linux/Git-based development, and familiarity with interfaces, computer architecture, and relevant semiconductor IP. This is a hybrid, non-remote position in Austin, Texas.

Develop and validate ASIC device drivers and test cases in C/C++ (Zephyr RTOS or Linux kernel), build Python frameworks and automation, assess and visualize test coverage, perform in-lab testing and platform/instrument setup, and collaborate with architects and cross-functional teams to improve validation methodology.

Leads the architecture and evolution of a back-end CAD framework for ASIC physical implementation. Develops advanced-node synthesis, place-and-route, timing closure, power optimization, signoff, automation, and AI-assisted design methodologies. Partners with physical design teams and EDA vendors, evaluates Synopsys and Cadence tools, improves power, performance, area, runtime, and productivity, and mentors engineers.

As a Senior AI Compiler Engineer, you will design and build a custom MLIR-based compiler stack for next-gen silicon, optimizing AI models without an OS. Responsibilities include creating MLIR dialects, ensuring accuracy in lowering computational graphs, and maintaining a high-performance compiler codebase.

As a Senior AI Compiler Engineer, you'll design and implement MLIR-based compilers for 5G/6G silicon, ensuring high precision in hardware-specific IR generation and memory management with a focus on advanced compiler techniques.

Designs, architects, implements, and verifies DFX, DFT, and silicon lifecycle management capabilities across ASIC programs. Responsibilities include DFT planning, production test strategy, in-field testing, telemetry, diagnostics, repair, post-silicon debug, yield bring-up, automation, and collaboration with physical design, test, CAD, EDA, and ASIC partner teams. The role also applies AI to engineering workflows and mentors junior engineers.

Build production-grade platforms and governance tooling for AI-assisted software development. Responsibilities include developing reusable standards, registries, APIs, developer tools, AI marketplaces, security and intellectual-property integrations, and CI/CD governance. The role partners across engineering and security teams, takes ambiguous problems from concept through production adoption, and measures platform impact, reliability, and developer experience.