Top Tech Jobs & Startup Jobs in Austin, TX

Serves as a senior technical authority for CPU physical implementation, RTL optimization, and power, performance, and area improvement. Leads Solution Engineering alignment, Cadence EDA strategy, process-node technology porting, implementation-flow enablement, and correlation across teams and partners. Establishes scalable methodologies, qualification models, governance, and diagnostic capabilities while influencing global stakeholders and vendors without direct authority.

Provide technical mentorship and support to partners integrating Arm CPUs and System IP into SoCs. Perform RTL simulation-based debugging, SoC build reviews, deliver training, influence IP development, test IP, and create knowledge-base content and tooling to improve partner outcomes.

Design and implement SystemVerilog RTL for memory controller functional units. Develop specifications and microarchitecture, collaborate with design and verification teams, debug functional and performance issues, and meet performance, power, and area targets. The role requires knowledge of DRAM standards, AMBA bus protocols, RTL design, synthesis, and design-quality checks such as lint and CDC analysis.

Develop and deploy Raven, a C++ dynamic random test generator for Arm CPU verification. Responsibilities include implementing verification functionality, creating test templates for architectural and microarchitectural features, debugging user and QA issues, collaborating with CPU verification engineers, and applying computer architecture specifications. The role requires strong C++ development, assembly programming, computer architecture knowledge, and familiarity with CPU verification environments.

Leads strategic UX research for AI and developer platforms, studying tools, APIs, runtimes, documentation, workflows, and agent-mediated experiences. The researcher identifies high-value questions, applies qualitative and quantitative methods, influences product and platform direction, and translates insights into design principles and recommendations. Responsibilities include engaging developers, customers, and partners; representing user needs in leadership and roadmap discussions; and mentoring peers to improve evidence-based research practices.

Develop cycle-accurate performance models for coherent and non-coherent Arm interconnects. Collaborate with micro-architects, RTL, validation teams, and customers to assess architectural trade-offs, develop features, build performance test suites, identify bottlenecks, and deliver data-driven system performance insights. The role requires strong C++, SystemC TLM, and Python skills, plus expertise in SoC performance modeling and computer architecture.

Design RTL logic for a coherent interconnect fabric using SystemVerilog. Collaborate with verification, implementation, performance, and power teams to deliver high-performance, low-power IP. Track and coordinate tasks, debug functional and performance issues with simulation and tools, and improve design methodology across the System IP group.

Develop and analyze memory controller IP and system performance models for Arm-based SoCs. Optimize power, performance, and microarchitecture using workload analysis, simulation, and emulation. Create performance methodologies, identify system bottlenecks, guide internal teams and partners, correlate models with RTL, and mentor engineers. Requires strong computer architecture expertise, C++ development, scripting, and experience with memory or interconnect performance modeling.

Lead the full-cycle technical recruiting process for engineering and semiconductor talent. Partner with hiring managers to define requirements, develop sourcing strategies, screen and interview candidates, manage offers, maintain recruiting data, and deliver a positive candidate experience. Advise senior stakeholders, support diversity and inclusion hiring goals, and contribute to employer branding, career events, and recruitment marketing initiatives.

Own end-to-end technical delivery for Arm’s engineering platforms, including requirements, planning, implementation, production support, and on-call incident response. Develop and maintain CI/CD, build, testing, cloud, containerization, infrastructure-as-code, and clustered computing solutions. Improve developer experience through automation, self-service infrastructure, and efficient engineering workflows.