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15 Days AgoSaved
Remote
United States
170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
The Senior ASIC Physical Design Engineer will oversee the full physical design flow for complex SoCs, ensuring timing closure and optimization while collaborating with various teams and external providers on satellite projects.
Top Skills: Cadence InnovusCpfDftFusion CompilerSynopsys Icc2Upf
15 Days AgoSaved
Remote
United States
190K-280K Annually
Senior level
190K-280K Annually
Senior level
Defense • Manufacturing
Lead the implementation of complex SoCs for satellite systems, managing the RTL-to-GDSII flow, collaborating with design teams, and ensuring silicon success in advanced technologies.
Top Skills: AsicCadenceGdsiiRtlSiemensSynopsys
Reposted 18 Days AgoSaved
Remote
United States
190K-285K Annually
Senior level
190K-285K Annually
Senior level
Defense • Manufacturing
The Principal ASIC Design Verification Engineer is responsible for verifying custom silicon designs, developing verification plans, and collaborating with cross-functional teams on design-for-verification practices and silicon validation.
Top Skills: CC++PerlPythonQuestaSimvisionSystemverilogTclUvmVcsVerdiXcelium
Reposted 18 Days AgoSaved
Remote
United States
170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
The Senior ASIC Design Verification Engineer will verify custom silicon designs, develop verification plans, drive test strategies, and collaborate with various engineering teams.
Top Skills: Ci/CdGitPerlPythonQuestaSimvisionSystemverilogTclUvmVcsVerdiXcelium
Reposted 18 Days AgoSaved
Remote
United States
130K-200K Annually
Mid level
130K-200K Annually
Mid level
Defense • Manufacturing
The ASIC Design Verification Engineer will verify silicon designs, develop verification plans, execute tests, and manage simulation environments, ensuring high quality and functionality through rigorous testing and collaboration with cross-functional teams.
Top Skills: GitPerlPythonQuestaSimvisionSystemverilogTclUvmVcsVerdiXcelium
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23 Days AgoSaved
Remote
United States
140K-200K Annually
Senior level
140K-200K Annually
Senior level
Defense • Manufacturing
The RFIC Layout Designer will lead the implementation of RF and mixed-signal ICs, focusing on layout strategies, top-level integration, and collaborating with various teams to ensure successful silicon tapeouts.
Top Skills: Eda ToolsFinfet TechnologiesMixed-Signal Integrated CircuitsPower PlanningRficSoc Design
23 Days AgoSaved
Remote
United States
170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
The Senior DFT Engineer will define and implement DFT architecture for mixed-signal SoCs, lead RTL-level DFT insertion, and collaborate with design teams to ensure high test coverage and manufacturability.
Top Skills: AtpgBistBoundary ScanDft ArchitectureJtagLow-Power DftMemory BistMixed-Signal SocsRtlScan InsertionTap ControllerTest Strategies
Reposted 24 Days AgoSaved
Remote
United States
200K-300K Annually
Senior level
200K-300K Annually
Senior level
Defense • Manufacturing
Lead a team of digital design engineers, manage ASIC design schedules, develop RTL for digital subsystems, and conduct verification and validation activities.
Top Skills: C++CadenceMatlabPythonSiemens ToolsSynopsysSystemverilogVerilog
Reposted 24 Days AgoSaved
Remote
United States
170K-250K Annually
Senior level
170K-250K Annually
Senior level
Defense • Manufacturing
Lead the design and implementation of digital subsystems for state-of-the-art wireless SoCs for satellites, optimizing for power, performance, and area.
Top Skills: C++MatlabPythonSystemverilogVerilog
Reposted 24 Days AgoSaved
Remote
United States
130K-200K Annually
Junior
130K-200K Annually
Junior
Defense • Manufacturing
Design and implement digital subsystems for advanced wireless SoCs; collaborate on mixed-signal SoCs tailored for satellite communications.
Top Skills: C++MatlabPythonSystemverilogVerilog
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